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micron parallel nor flash embedded memory (p30-65nm) js28f256p30b/tfx, rc28f256p30b/tfx, pc28f256p30b/tfx, rd48f4400p0vbqex, rc48f4400p0vb0ex, pc48f4400p0vb0ex, pf48f4000p0zb/tqex features ? high performance C 100ns initial access for easy bga C 110ns initial access for tsop C 25ns 16-word asychronous page read mode C 52 mhz (easy bga) with zero wait states and 17ns clock-to-data output synchronous burst read mode C 4-, 8-, 16-, and continuous word options for burst mode C buffered enhanced factory programming (befp) at 2 mb/s (typ) using a 512-word buffer C 1.8v buffered programming at 1.14 mb/s (typ) using a 512-word buffer ? architecture C mlc: highest density at lowest cost C asymmetrically blocked architecture C four 32kb parameter blocks: top or bottom con- figuration C 128kb main blocks C blank check to verify an erased block ? voltage and power C v cc (core) voltage: 1.7v to 2.0v C v ccq (i/o) voltage: 1.7v to 3.6v C standy current: 65a (typ) for 256mb C 52 mhz continuous synchronous read current: 21ma (typ), 24ma (max) ? security C one-time programmable register: 64 otp bits, programmed with unique information from mi- cron; 2112 otp bits available for customer pro- gramming C absolute write protection: v pp = v ss C power-transition erase/program lockout C individual zero-latency block locking C individual block lock-down C password access ? software C 25 s (typ) program suspend C 25 s (typ) erase suspend C flash data integrator optimized C basic command set and extended function inter- face (efi) command set compatible C common flash interface ? density and packaging C 56-lead tsop package (256mb only) C 64-ball easy bga package (256mb, 512mb) C quad+ and scsp packages (256mb, 512mb) C 16-bit wide data bus ? quality and reliabilty C jesd47 compliant C operating temperature: C40c to +85c C minimum 100,000 erase cycles per block C 65nm process technology 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
discrete and mcp part numbering information devices are shipped from the factory with memory content bits erased to 1. for available options, such as pack- ages or for further information, contact your micron sales representative. part numbers can be verified at www.mi- cron.com . feature and specification comparison by device type is available at www.micron.com/products . con- tact the factory for devices not found. note: not all part numbers listed here are available for ordering. table 1: discrete part number information part number category category details package js = 56-lead tsop, lead free pc = 64-ball easy bga, lead-free rc = 64-ball easy bga, leaded product line 28f = micron flash memory density 256 = 256mb product family p30 (vcc = 1.7 to 2.0v; vccq = 1.7 to 3.6v) parameter location b/t = bottom/top parameter lithography f = 65nm features * note: 1. the last digit is assigned randomly to cover packaging media, features, or other specific configuration infor- mation. sample part number: js28f256p30bf* 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 2: mcp part number information part number category category details package rd = micron mcp, leaded pf = micron mcp, lead-free rc = 64-ball easy bga, leaded pc = 64-ball easy bga, lead-free product line 48f = micron flash memory only density 0 = no die 4 = 256mb product family p = micron flash memory (p30) 0 = no die io voltage and chip configuration z = individual chip enables v = virtual chip enables vcc = 1.7 to 2.0v; vccq = 1.7 to 3.6v parameter location b/t = bottom/top parameter ballout q = quad+ 0 = discrete lithography e = 65nm features * note: 1. the last digit is assigned randomly to cover packaging media, features, or other specific configuration infor- mation. sample part number: rc48f4400p0vb0e* table 3: discrete and mcp part combinations package density packing media boot configuration 1 part number js 256mb tray b js28f256p30bfe tape and reel js28f256p30bff tray t js28f256p30tfe pc 256mb tray b pc28f256p30bfe tape and reel pc28f256p30bff tray t pc28f256p30tfe 512mb (256mb/256mb) tray b/t pc48f4400p0vb0ee tape and reel pc48f4400p0vb0ef pf 256mb tray b pf48f4000p0zbqef tray t pf48f4000p0ztqej 512mb (256mb/256mb) tray b/t pf48f4400p0vbqef tape and reel pf48f4400p0vbqek 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 3: discrete and mcp part combinations (continued) package density packing media boot configuration 1 part number rc 256mb tray b rc28f256p30bfe tray t rc28f256p30tfe tape and reel rc28f256p30tff 512mb (256mb/256mb) tray b/t rc48f4400p0vb0ej rd 512mb (256mb/256mb) tray b/t rd48f4400p0vbqej note: 1. bottom boot/top boot = b/t table 4: otp feature part combinations package density packing media boot configuration 1 part number js C C C C pc 256mb tape and reel b pc28f256p30bfr pf C C C C rc C C C C rd C C C C notes: 1. this data sheet covers only standard parts. for otp parts, contact your local micron representative. 2. bottom boot/top boot = b/t 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 9 virtual chip enable description ........................................................................................................................ 9 memory map ................................................................................................................................................. 12 package dimensions ....................................................................................................................................... 13 pinouts and ballouts ....................................................................................................................................... 17 signal descriptions ......................................................................................................................................... 21 bus operations ............................................................................................................................................... 24 read .......................................................................................................................................................... 24 write .......................................................................................................................................................... 24 output disable ........................................................................................................................................... 24 standby ..................................................................................................................................................... 24 reset .......................................................................................................................................................... 25 device command codes ................................................................................................................................. 26 device command bus cycles .......................................................................................................................... 29 read operations ............................................................................................................................................. 31 asynchronous page mode read ................................................................................................................... 31 asynchronous single word read ................................................................................................................. 31 synchronous burst mode read ................................................................................................................... 32 read cfi .................................................................................................................................................... 32 read device id ........................................................................................................................................... 32 device id codes ............................................................................................................................................. 33 program operations ....................................................................................................................................... 34 word programming (40h) ........................................................................................................................... 34 buffered programming (e8h, d0h) .............................................................................................................. 34 buffered enhanced factory programming (80h, d0h) ................................................................................... 35 program suspend ....................................................................................................................................... 37 program resume ........................................................................................................................................ 38 program protection .................................................................................................................................... 38 erase operations ............................................................................................................................................ 39 block erase command ........................................................................................................................... 39 blank check command .......................................................................................................................... 39 erase suspend command ....................................................................................................................... 40 erase resume command ........................................................................................................................ 40 erase protection ......................................................................................................................................... 40 security operations ........................................................................................................................................ 41 block locking ............................................................................................................................................. 41 block lock command ............................................................................................................................ 41 block unlock command ....................................................................................................................... 41 block lock down command ................................................................................................................. 41 block lock status ....................................................................................................................................... 41 block locking during suspend ................................................................................................................... 42 selectable otp blocks ................................................................................................................................. 43 password access ......................................................................................................................................... 43 status register ................................................................................................................................................ 44 read status register ................................................................................................................................... 44 clear status register ................................................................................................................................... 45 configuration register .................................................................................................................................... 46 read configuration register ....................................................................................................................... 46 read mode ................................................................................................................................................. 46 latency count ............................................................................................................................................ 47 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
end of wordline considerations .................................................................................................................. 48 wait signal polarity and functionality ........................................................................................................ 49 wait delay ................................................................................................................................................ 50 burst sequence .......................................................................................................................................... 50 clock edge ................................................................................................................................................. 51 burst wrap ................................................................................................................................................. 51 burst length .............................................................................................................................................. 51 one-time programmable registers ................................................................................................................. 52 read otp registers ..................................................................................................................................... 52 program otp registers ............................................................................................................................... 53 lock otp registers ..................................................................................................................................... 53 common flash interface ................................................................................................................................ 55 read cfi structure output ........................................................................................................................ 55 flowcharts ..................................................................................................................................................... 68 power and reset specifications ....................................................................................................................... 77 power supply decoupling ........................................................................................................................... 78 maximum ratings and operating conditions .................................................................................................. 79 dc electrical specifications ............................................................................................................................ 80 ac test conditions and capacitance ............................................................................................................... 82 ac read specifications ................................................................................................................................... 84 ac write specifications ................................................................................................................................... 91 program and erase characteristics .................................................................................................................. 97 revision history ............................................................................................................................................. 98 rev. c C 12/13 ............................................................................................................................................. 98 rev. b C 8/13 ............................................................................................................................................... 98 rev. a C 10/12 ............................................................................................................................................. 98 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of figures figure 1: 512mb easy bga block diagram ...................................................................................................... 10 figure 2: 512mb quad+ block diagram ......................................................................................................... 11 figure 3: memory map C 256mb and 512mb ................................................................................................... 12 figure 4: 56-pin tsop C 14mm x 20mm .......................................................................................................... 13 figure 5: 64-ball easy bga C 10mm x 13mm x 1.2mm ...................................................................................... 14 figure 6: 88-ball quad+ C 8mm x 11mm x 1.0mm: 256mb only ...................................................................... 15 figure 7: 88-ball quad+ C 8mm x 11mm x 1.2mm: 512mb only ...................................................................... 16 figure 8: 56-lead tsop pinout C 256mb ......................................................................................................... 17 figure 9: 64-ball easy bga ballout C 256mb, 512mb ........................................................................................ 18 figure 10: quad+ mcp ballout ..................................................................................................................... 20 figure 11: example v pp supply connections ................................................................................................... 38 figure 12: block locking state diagram .......................................................................................................... 42 figure 13: first access latency count ............................................................................................................ 47 figure 14: example latency count setting using code 3 ................................................................................. 48 figure 15: end of wordline timing diagram ................................................................................................... 48 figure 16: otp register map .......................................................................................................................... 53 figure 17: word program procedure ............................................................................................................... 68 figure 18: buffer program procedure .............................................................................................................. 69 figure 19: buffered enhanced factory programming (befp) procedure ........................................................... 70 figure 20: block erase procedure ................................................................................................................... 71 figure 21: program suspend/resume procedure ............................................................................................ 72 figure 22: erase suspend/resume procedure ................................................................................................. 73 figure 23: block lock operations procedure ................................................................................................... 74 figure 24: otp register programming procedure ............................................................................................ 75 figure 25: status register procedure .............................................................................................................. 76 figure 26: reset operation waveforms ........................................................................................................... 78 figure 27: ac input/output reference timing ................................................................................................ 82 figure 28: transient equivalent load circuit .................................................................................................. 82 figure 29: clock input ac waveform .............................................................................................................. 82 figure 30: asynchronous single-word read (adv# low) ................................................................................ 86 figure 31: asynchronous single-word read (adv# latch) ............................................................................... 86 figure 32: asynchronous page mode read ...................................................................................................... 87 figure 33: synchronous single-word array or nonarray read .......................................................................... 88 figure 34: continuous burst read with output delay ..................................................................................... 89 figure 35: synchronous burst mode 4-word read ........................................................................................... 90 figure 36: write to write timing .................................................................................................................... 93 figure 37: asynchronous read to write timing ............................................................................................... 93 figure 38: write to asynchronous read timing ............................................................................................... 94 figure 39: synchronous read to write timing ................................................................................................ 95 figure 40: write to synchronous read timing ................................................................................................ 96 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of tables table 1: discrete part number information ...................................................................................................... 2 table 2: mcp part number information ........................................................................................................... 3 table 3: discrete and mcp part combinations .................................................................................................. 3 table 4: otp feature part combinations .......................................................................................................... 4 table 5: virtual chip enable truth table for 512mb (quad+ package) ............................................................. 10 table 6: virtual chip enable truth table for 512mb (easy bga packages) ........................................................ 10 table 7: tsop and easy bga signal descriptions ............................................................................................ 21 table 8: quad+ scsp signal descriptions ...................................................................................................... 22 table 9: bus operations ................................................................................................................................. 24 table 10: command codes and definitions .................................................................................................... 26 table 11: command bus cycles ..................................................................................................................... 29 table 12: device id information .................................................................................................................... 32 table 13: device id codes .............................................................................................................................. 33 table 14: befp requirements ........................................................................................................................ 36 table 15: befp considerations ...................................................................................................................... 36 table 16: status register description .............................................................................................................. 44 table 17: read configuration register ............................................................................................................ 46 table 18: end of wordline data and wait state comparison ........................................................................... 49 table 19: wait functionality table ................................................................................................................ 49 table 20: burst sequence word ordering ........................................................................................................ 50 table 21: example of cfi output (x16 device) as a function of device and mode ............................................. 55 table 22: cfi database: addresses and sections ............................................................................................. 56 table 23: cfi id string ................................................................................................................................... 56 table 24: system interface information .......................................................................................................... 57 table 25: device geometry ............................................................................................................................ 58 table 26: block region map information ........................................................................................................ 58 table 27: primary vendor-specific extended query ........................................................................................ 59 table 28: optional features field ................................................................................................................... 60 table 29: one time programmable (otp) space information .......................................................................... 60 table 30: burst read information ................................................................................................................... 61 table 31: partition and block erase region information .................................................................................. 62 table 32: partition region 1 information: top and bottom offset/address ....................................................... 63 table 33: partition region 1 information ........................................................................................................ 63 table 34: partition region 1: partition and erase block map information ......................................................... 66 table 35: cfi link information ...................................................................................................................... 67 table 36: additional cfi link field ................................................................................................................. 67 table 37: power and reset .............................................................................................................................. 77 table 38: maximum ratings ........................................................................................................................... 79 table 39: operating conditions ...................................................................................................................... 79 table 40: dc current characteristics .............................................................................................................. 80 table 41: dc voltage characteristics .............................................................................................................. 81 table 42: test configuration: worst-case speed condition .............................................................................. 82 table 43: capacitance .................................................................................................................................... 83 table 44: ac read specifications .................................................................................................................... 84 table 45: ac write specifications ................................................................................................................... 91 table 46: program and erase specifications .................................................................................................... 97 256mb and 512mb (256mb/256mb), p30-65nm features pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
general description the micron parallel nor flash memory is the latest generation of flash memory devi- ces. benefits include more density in less space, high-speed interface device, and sup- port for code and data storage. features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. the product family is manufactured using mi- cron 65nm process technology. the nor flash device provides high performance at low voltage on a 16-bit data bus. individually erasable memory blocks are sized for optimum code and data storage. upon initial power up or return from reset, the device defaults to asynchronous page- mode read. configuring the read configuration register enables synchronous burst- mode reads. in synchronous burst mode, output data is synchronized with a user-sup- plied clock signal. a wait signal provides easy cpu-to-flash memory synchronization. in addition to the enhanced architecture and interface, the device incorporates technol- ogy that enables fast factory program and erase operations. designed for low-volt- age systems, the device supports read operations with v cc at the low voltages, and erase and program operations with v pp at the low voltages or v pph . buffered en- hanced factory programming (befp) provides the fastest flash array programming per- formance with v pp at v pph , which increases factory throughput. with v pp at low voltag- es, v cc and v pp can be tied together for a simple, ultra low-power design. in addition to voltage flexibility, a dedicated v pp connection provides complete data protection when v pp v pplk . a command user interface is the interface between the system processor and all inter- nal operations of the device. the device automatically executes the algorithms and tim- ings necessary for block erase and program. a status register indicates erase or pro- gram completion and any errors that may have occurred. an industry-standard command sequence invokes program and erase automation. each erase operation erases one block. the erase suspend feature enables system soft- ware to pause an erase cycle to read or program data in another block. program sus- pend enables system software to pause programming to read other locations. data is programmed in word increments (16 bits). the protection register enables unique device identification that can be used to in- crease system security. the individual block lock feature provides zero-latency block locking and unlocking. the device includes enhanced protection via password access; this new feature supports write and/or read access protection of user-defined blocks. in addition, the device also provides the full-device otp security feature. virtual chip enable description the 512mb device employs a virtual chip enable feature, which combines two 256mb die with a common chip enable, f1-ce# for quad+ packages, or ce# for easy bga packages. the maximum address bit is then used to select between the die pair with f1- ce#/ce# asserted, depending upon the package option used. when f1-ce#/ce# is as- serted and the maximum address bit is low, the lower parameter die is selected; when f1-ce#/ce# is asserted and the maximum address bit is high, the upper parameter die is selected. 256mb and 512mb (256mb/256mb), p30-65nm general description pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 5: virtual chip enable truth table for 512mb (quad+ package) die selected f1-ce# a24 lower param die l l upper param die l h table 6: virtual chip enable truth table for 512mb (easy bga packages) die selected ce# a25 lower param die l l upper param die l h figure 1: 512mb easy bga block diagram parameter configuration easy bga (dual die) top/bottom bottom parameter die top parameter die ce# a[max:1] adv# clk we# oe# wp# wait dq[15:0] rst# v pp v ccq v cc v ss 256mb and 512mb (256mb/256mb), p30-65nm virtual chip enable description pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 2: 512mb quad+ block diagram parameter configuration quad+ 512mb (dual die) top/bottom bottom parameter die 256mb top parameter die 256mb f1-ce# a[max:0] adv# clk we# oe# wp# wait dq[15:0] rst# v pp v ccq v cc v ss 256mb and 512mb (256mb/256mb), p30-65nm virtual chip enable description pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
memory map figure 3: memory map C 256mb and 512mb ff0000 - ff3fff ff4000 - ff7fff ff8000 - ffbfff ffc000 - ffffff fe0000 - feffff 16 kword block 255 16 kword block 256 16 kword block 257 16 kword block 258 64 kword block 254 010000 - 01ffff 000000 - 00ffff 64 kword block 1 64 kword block 0 top boot 256mb, world-wide x16 mode a[24:1] 256mb, easy bga, tsop a[23:0] 256mb, quad+ 3f0000 - 3fffff 7f0000 - 7fffff ff0000 - ffffff 000000 - 003fff 004000 - 007fff 008000 - 00bfff 00c000 - 00ffff 010000 - 01ffff 020000 - 02ffff 16 kword block 0 16 kword block 1 16 kword block 2 16 kword block 3 64 kword block 4 64 kword block 5 64 kword block 130 64 kword block 258 64 kword block 66 bottom boot 256mb, world-wide x16 mode a[24:1] 256mb, easy bga, tsop a[23:0] 256mb, quad+ 256mb 256mb 000000 - 003fff 004000 - 007fff 008000 - 00bfff 00c000 - 00ffff 010000 - 01ffff 020000 - 02ffff 16 kword block 0 16 kword block 1 16 kword block 2 16 kword block 3 64 kword block 4 64 kword block 5 1ff0000 - 1ff3fff 1ff4000 - 1ff7fff 1ff8000 - 1ffbfff 1ffc000 - 1ffffff 1fe0000 - 1feffff 1fd0000 - 1fdffff 16 kword block 514 16 kword block 515 16 kword block 516 16 kword block 517 64 kword block 513 64 kword block 512 a[25:1] 512mb (256mb/256mb), easy bga, tsop a[24:0] 512mb (256mb/256mb), quad+ 512mb (256mb/256mb), world wide x16 mode 512mb (256mb/256mb) 256mb and 512mb (256mb/256mb), p30-65nm memory map pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
package dimensions figure 4: 56-pin tsop C 14mm x 20mm see detail a 0.5 typ 14.00 0.2 0.25 0.1 1.20 max 18.4 0.2 0.995 0.03 20 0.2 0.22 0.05 detail a 0.60 0.10 0.05 min 0.10 seating plane pin #1 index see notes 2 see note 2 see note 2 see note 2 0.15 0.05 3 +2 -3 notes: 1. all dimensions are in millimeters. drawing not to scale. 2. one dimple on package denotes pin 1; if two dimples, then the larger dimple denotes pin 1. pin 1 will always be in the upper left corner of the package, in reference to the product mark. 3. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 256mb and 512mb (256mb/256mb), p30-65nm package dimensions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 5: 64-ball easy bga C 10mm x 13mm x 1.2mm ball a1 id 0.78 typ 0.25 min seating plane 0.1 1.20 max 1.00 typ a b c d e f g h 8 7 6 5 4 3 2 1 3.0 0.1 10 0.1 64x ?0.43 0.1 1.00 typ 13 0.1 1.5 0.1 ball a1 id note: 1. all dimensions are in millimeters. drawing not to scale. 256mb and 512mb (256mb/256mb), p30-65nm package dimensions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 6: 88-ball quad+ C 8mm x 11mm x 1.0mm: 256mb only top view - ball down bottom view - ball up a c b e d g f j h k l m 1 2 3 4 5 6 7 8 a c b e d g f j h k l m 1 2 3 4 5 6 7 8 1.00 max 0.10 max 0.20 min 0.740 typ 0.80 typ 0.375 0.05 1.20 0.10 1.10 0.10 11.00 0.10 8.00 0.10 note: 1. all dimensions are in millimeters. drawing not to scale. 256mb and 512mb (256mb/256mb), p30-65nm package dimensions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 7: 88-ball quad+ C 8mm x 11mm x 1.2mm: 512mb only top view - ball down bottom view - ball up a c b e d g f j h k l m 1 2 3 4 5 6 7 8 a c b e d g f j h k l m 1 2 3 4 5 6 7 8 1.20 max 0.10 max 0.20 min 0.860 typ 0.80 typ 0.375 0.050 1.20 0.10 1.10 0.10 11.00 0.10 8.00 0.10 note: 1. all dimensions are in millimeters. drawing not to scale. 256mb and 512mb (256mb/256mb), p30-65nm package dimensions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
pinouts and ballouts figure 8: 56-lead tsop pinout C 256mb 56-lead tsop pinout 14mm x 20mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a 14 a 13 a 12 a 10 a 9 a 11 vss a 23 a 21 a 22 rfu wp # a 20 we # a 19 a 8 a 7 a 18 a 6 a 4 a 3 a 5 a 2 rfu vss a 24 wait dq 15 dq 7 a 17 dq 14 dq 13 dq 5 dq 6 dq 12 adv # clk dq 4 rst # a 16 dq 3 vpp dq 10 vccq dq 9 dq 2 dq 1 dq 0 vcc dq 8 oe # ce # a 1 vss a 15 dq 11 notes: 1. a1 is the least significant address bit. 2. a24 is valid for 256mb densities; otherwise, it is a no connect (nc). 3. no internal connection on pin 13; it may be driven or floated. for legacy designs, it is a v cc pin and can be tied to v cc . 4. one dimple on package denotes pin 1 which will always be in the upper left corner of the package, in reference to the product mark. 256mb and 512mb (256mb/256mb), p30-65nm pinouts and ballouts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 9: 64-ball easy bga ballout C 256mb, 512mb 1 8 2 3 4 5 6 7 h g f e d c a a 2 v ss a 9 a 14 ce # a 19 rfu a 25 rfu v ss v cc dq 13 v ss dq 7 a 24 vss a 3 a 7 a 10 a 15 a 12 a 20 a 21 wp # a 4 a 5 a 11 v ccq rst # a 16 a 17 v ccq rfu dq 8 dq 1 dq 9 dq 4 dq 3 dq 15 clk rfu oe # dq 0 dq 10 dq 12 dq 11 wait adv # we # a 23 rfu dq 2 dq 5 v ccq dq 14 dq 6 a 1 a 6 a 8 a 13 v pp a 18 a 22 v cc b 256mb and 512mb (256mb/256mb), p30-65nm pinouts and ballouts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
notes: 1. a1 is the least significant address bit. 2. a24 is valid for 256mb densities and above; otherwise, it is a no connect (nc). 3. a25 is valid for 512mb densities; otherwise, it is a no connect. 4. one dimple on package denotes a1 pin, which will always be in the upper-left corner of the package, in reference to the product mark. 256mb and 512mb (256mb/256mb), p30-65nm pinouts and ballouts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 10: quad+ mcp ballout pin 1 1 2 3 4 5 6 7 8 a du du depop depop depop depop du du a b a 4 a 18 a 19 vss vcc vcc a 21 a 11 b c a 5 rfu a 23 vss rfu clk a 22 a 12 c d a 3 a 17 a 24 vpp rfu rfu a 9 a 13 d e a 2 a 7 wp # adv # a 20 a 10 a 15 e f a 1 a 6 rfu rst # we # a 8 a 14 a 16 f g a 0 dq 8 dq 2 dq 10 dq 5 dq 13 wait f 2 - ce # g h rfu dq 0 dq 1 dq 3 dq 12 dq 14 dq 7 f 2 - oe # h j rfu f1-oe# dq 9 dq 11 dq 4 dq 6 dq 15 vccq j k f 1 - ce # rfu rfu rfu rfu vcc vccq rfu k l vss vss vccq vcc vss vss vss vss l m du du depop depop depop depop du du m 1 2 3 4 5 6 7 8 control signals reserved for future use data do not use power / ground address top view - ball side down legends : de - populated ball rfu notes: 1. a23 is valid for 256mb densities and above; otherwise, it is a no connect. 2. a24 is valid for 512mb densities and above; otherwise, it is a no connect. 3. f2-ce# and f2-oe# are no connect for all densities. 4. a0 is lsb for address. 256mb and 512mb (256mb/256mb), p30-65nm pinouts and ballouts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal descriptions table 7: tsop and easy bga signal descriptions symbol type name and function a[max:1] input address inputs: device address inputs. note: unused active address pins should not be left floating; tie them to v ccq or v ss ac- cording to specific design requirements. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, which- ever occurs first. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low. note: designs not using adv# must tie it to v ss to allow addresses to flow through. ce# input chip enable: active low input. ce# low selects the associated die. when asserted, inter- nal control logic, input buffers, decoders, and sense amplifiers are active. when de-asser- ted, the associated die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z. note: ce# must be driven high when device is not in use. clk input clock: synchronizes the device with the system bus frequency in synchronous-read mode. during synchronous reads, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. note: designs not using clk for synchronous read mode must tie it to v ccq or v ss . oe# input output enable: active low input. oe# low enables the devices output data buffers during read cycles. oe# high places the data outputs and wait in high-z. rst# input reset: active low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal opera- tion. exit from reset places the device in asynchronous read array mode. wp# input write protect: active low input. wp# low enables the lock-down mechanism. blocks in lock-down cannot be unlocked with the unlock command. wp# high overrides the lock- down function enabling blocks to be erased or programmed using software commands. note: designs not using wp# for protection could tie it to v ccq or v ss without additional capacitor. we# input write enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we# or ce#, whichever occurs first. v pp power/input erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl,min . v pp must remain above v ppl,min to perform in-system modification. v pp may be 0v during read op- erations. v pp can be connected to 9v for a cumulative total not to exceed 80 hours. extended use of this pin at 9v may reduce block cycling capability. dq[15:0] input/output data input/output: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are de-asserted. data is internally latched during writes. 256mb and 512mb (256mb/256mb), p30-65nm signal descriptions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 7: tsop and easy bga signal descriptions (continued) symbol type name and function wait output wait: indicates data valid in synchronous array or non-array burst reads. read configura- tion register bit 10 (rcr.10, wt) determines its polarity when asserted. this signal's active output is v ol or v oh when ce# and oe# are v il . wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, this signal indicates invalid data when as- serted and valid data when de-asserted. ? in asynchronous page mode, and all write modes, this signal is de-asserted. v cc power device core power supply: core (logic) source voltage. writes to the array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. v ccq power output power supply: output-driver source voltage. v ss power ground: connect to system ground. do not float any v ss connection. rfu reserved for future use: reserved by micron for future device functionality and en- hancement. these should be treated in the same way as a du signal. du do not use: do not connect to any other signal, or power supply; must be left floating. nc no connect: no internal connection; can be driven or floated. table 8: quad+ scsp signal descriptions symbol type name and function a[max:0] input address inputs: device address inputs. 256mb: a[23:0]; 512mb: a[24:0]. note: the virtual selection of the 256mb top parameter die in the dual-die 512mb configuration is accom- plished by setting a24 high. note: the address pins unused in design should not be left floating; tie them to v ccq or v ss according to specific design requirements. note: when handling the quad + scsp package, note that lsb is a0; address conversion is necessary. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, which- ever occurs first. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low. note: designs not using adv# must tie it to v ss to allow addresses to flow through. f1-ce# input flash chip enable: active low input. f1-ce# low selects the associated die. when asser- ted, internal control logic, input buffers, decoders, and sense amplifiers are active. when de-asserted, the associated die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z. note: f1-ce# must be driven high when device is not in use. clk input clock: synchronizes the device with the system bus frequency in synchronous-read mode. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. note: designs not using clk for synchronous read mode must tie it to v ccq or v ss . f1-oe# input output enable: active low input. f1-oe# low enables the devices output data buffers during read cycles. f1-oe# high places the data outputs and wait in high-z. 256mb and 512mb (256mb/256mb), p30-65nm signal descriptions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 8: quad+ scsp signal descriptions (continued) symbol type name and function rst# input reset: active low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal opera- tion. exit from reset places the device in asynchronous read array mode. we# input write enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we# or ce#, whichever occurs first. wp# input write protect: active low input. wp# low enables the lock-down mechanism. blocks in lock-down cannot be unlocked with the unlock command. wp# high overrides the lock- down function enabling blocks to be erased or programmed using software commands. note: designs not using wp# for protection could tie it to v ccq or v ss without additional capacitor. v pp power/lnput erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl,min . v pp must remain above v ppl,min to perform in-system flash modification. v pp may be 0v during read operations. v pph can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. v pp can be connected to 9v for a cumulative total not to exceed 80 hours. ex- tended use of this pin at 9v may reduce block cycling capability. dq[15:0] input/output data input/output: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are de-asserted. data is internally latched during writes. wait output wait: indicates data valid in synchronous array or non-array burst reads. read configura- tion register bit 10 (rcr.10, wt) determines its polarity when asserted. the active output is v ol or v oh when ce# and oe# are v il . wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asser- ted and valid data when de-asserted. ? in asynchronous page mode, and all write modes, wait is de-asserted. v cc power device core power supply: core (logic) source voltage. writes to the array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. v ccq power output power supply: output driver source voltage. v ss power ground: connect to system ground. do not float any v ss connection. rfu reserved for future use: reserved by micron for future device functionality and en- hancement. these should be treated in the same way as a du signal. du do not use: do not connect to any other signal, or power supply; must be left floating. nc no connect: no internal connection; can be driven or floated. 256mb and 512mb (256mb/256mb), p30-65nm signal descriptions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bus operations ce# low and rst# high enable read operations. the device internally decodes up- per address inputs to determine the accessed block. adv# low opens the internal ad- dress latches. oe# low activates the outputs and gates selected data onto the i/o bus. bus cycles to/from the device conform to standard microprocessor bus operations. bus operations and the logic levels that must be applied to the device control signal inputs are shown here. table 9: bus operations bus operation rst# clk adv# ce# oe# we# wait dq[15:0] notes read asynchronous h x l l l h de-asserted output - synchronous h run- ning l l l h driven output - write h x l l h l high-z input 1 output disable h x x l h h high-z high-z 2 standby h x x h x x high-z high-z 2 reset l x x x x x high-z high-z 2, 3 notes: 1. refer to the device command bus cycles for valid dq[15:0] during a write operation. 2. x = "dont care" (h or l). 3. rst# must be at v ss 0.2v to meet the maximum specified power-down current. read to perform a read operation, rst# and we# must be de-asserted while ce# and oe# are asserted. ce# is the device-select control. when asserted, it enables the device. oe# is the data-output control. when asserted, the addressed flash memory data is driven onto the i/o bus. write to perform a write operation, both ce# and we# are asserted while rst# and oe# are de-asserted. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. the command bus cycles table shows the bus cycle sequence for each of the supported device commands, while the command codes and definitions table describes each command. note: write operations with invalid v cc and/or v pp voltages can produce spurious re- sults and should not be attempted. output disable when oe# is de-asserted, device outputs dq[15:0] are disabled and placed in high-z state, wait is also placed in high-z. standby when ce# is de-asserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, inde- pendent of the level placed on oe#. standby current (i ccs ) is the average current meas- 256mb and 512mb (256mb/256mb), p30-65nm bus operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ured over any 5ms time interval, 5 s after ce# is de-asserted. during standby, average current is measured over the same time interval 5 s after ce# is de-asserted. when the device is deselected (while ce# is de-asserted) during a program or erase operation, it continues to consume active power until the program or erase opera- tion is completed. reset as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the system processor attempts to read from the device if it is the system boot device. if a cpu reset occurs with no device reset, improp- er cpu initialization may occur because the device may be providing status informa- tion rather than array data. micron devices enable proper cpu initialization following a system reset through the use of the rst# input. rst# should be controlled by the same low-true reset signal that resets the system cpu. after initial power-up or reset, the device defaults to asynchronous read array mode, and the status register is set to 0x80. asserting rst# de-energizes all internal circuits, and places the output drivers in high-z. when rst# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to com- plete. when rst# has been de-asserted, the device is reset to asynchronous read array state. when device returns from a reset (rst# de-asserted), a minimum wait is required be- fore the initial read access outputs valid data. also, a minimum delay is required after a reset before a write cycle can be initiated. after this wake-up interval passes, normal op- eration is restored. note: if rst# is asserted during a program or erase operation, the operation is ter- minated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. 256mb and 512mb (256mb/256mb), p30-65nm bus operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device command codes the system cpu provides control of all in-system read, write, and erase operations of the device via the system bus. the device manages all block-erase and word-program algorithms. device commands are written to the cui to control all device operations. the cui does not occupy an addressable memory location; it is the mechanism through which the device is controlled. note: for a dual device, all setup commands should be re-issued to the device when a different die is selected. table 10: command codes and definitions mode device mode code description read read array 0xff places the device in read array mode. array data is output on dq[15:0]. read status register 0x70 places the device in read status register mode. the device enters this mode after a program or erase command is issued. status register data is output on dq[7:0]. read device id or read configuration register 0x90 places device in read device identifier mode. subsequent reads output manufacturer/device codes, configuration register data, block lock sta- tus, or protection register data on dq[15:0]. read cfi 0x98 places the device in read cfi mode. subsequent reads output cfi infor- mation on dq[7:0]. clear status register 0x50 the device sets status register error bits. the clear status register com- mand is used to clear the sr error bits. write word program setup 0x40 first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the device executes the programming algorithm at the ad- dressed location. during program operations, the device responds only to read status register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchro- nous read. ce# or adv# must be toggled to update the status register data for synchronous non-array reads. the read array command must be issued to read array data after programming has finished. buffered program 0xe8 this command loads a variable number of words up to the buffer size of 512 words onto the program buffer. buffered program confirm 0xd0 the confirm command is issued after the data streaming for writing into the buffer is completed. the device then performs the buffered program algorithm, writing the data from the buffer to the memory array. befp setup 0x80 first cycle of a two-cycle command; initiates buffered enhanced factory program mode (befp). the cui then waits for the befp confirm com- mand, 0xd0, that initiates the befp algorithm. all other commands are ignored when befp mode begins. befp confirm 0xd0 if the previous command was befp setup (0x80), the cui latches the address and data, and prepares the device for befp mode. 256mb and 512mb (256mb/256mb), p30-65nm device command codes pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 10: command codes and definitions (continued) mode device mode code description erase block erase setup 0x20 first cycle of a two-cycle command; prepares the cui for a block erase operation. the device performs the erase algorithm on the block addressed by the erase confirm command. if the next com- mand is not the erase confirm (0xd0) command, the cui sets status register bits sr4 and sr5, and places the device in read status register mode. block erase confirm 0xd0 if the first command was block erase setup (0x20), the cui latches the address and data, and the device erases the addressed block. dur- ing block erase operations, the device responds only to read status register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-ar- ray reads. suspend program or erase suspend 0xb0 this command issued to any device address initiates a suspend of the currently-executing program or block erase operation. the status register indicates successful suspend operation by setting either sr2 (program suspended) or sr6 (erase suspended), along with sr7 (ready). the device remains in the suspend mode regardless of control signal states (except for rst# asserted). suspend resume 0xd0 this command issued to any device address resumes the suspended program or block erase operation. protection block lock setup 0x60 first cycle of a two-cycle command; prepares the cui for block lock con- figuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock down (0x2f), the cui sets sta- tus register bits sr5 and sr4, indicating a command sequence error. block lock 0x01 if the previous command was block lock setup (0x60), the addressed block is locked. block unlock 0xd0 if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock down state, the op- eration has no effect. block lock down 0x2f if the previous command was block lock setup (0x60), the addressed block is locked down. otp register or lock register program set- up 0xc0 first cycle of a two-cycle command; prepares the device for a otp reg- ister or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm to program data the otp array. configuration read configuration register setup 0x60 first cycle of a two-cycle command; prepares the cui for device read configuration. if the set read configuration register command (0x03) is not the next command, the cui sets status register bits sr4 and sr5, indicating a command sequence error. read configuration register 0x03 if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[16:1] to the read con- figuration register for easy bga and tsop, a[15:0] for quad+. follow- ing a configure read configuration register command, subse- quent read operations access array data. 256mb and 512mb (256mb/256mb), p30-65nm device command codes pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 10: command codes and definitions (continued) mode device mode code description blank check block blank check 0xbc first cycle of a two-cycle command; initiates the blank check opera- tion on a main block. block blank check confirm 0xd0 second cycle of blank check command sequence; it latches the block address and executes blank check on the main array block. efi extended function interface 0xeb first cycle of a multiple-cycle command; initiate operation using exten- ded function interface. the second cycle is a sub-op-code, the data written on third cycle is one less than the word count; the allowable value on this cycle are 0C511. the subsequent cycles load data words in- to the program buffer at a specified address until word count is ach- ieved. 256mb and 512mb (256mb/256mb), p30-65nm device command codes pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device command bus cycles device operations are initiated by writing specific device commands to the command user interface (cui). several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally timed functions that culminate in the completion of the re- quested task. however, the operation can be aborted by either asserting rst# or by is- suing an appropriate suspend command. table 11: command bus cycles mode command bus cycles first bus cycle second bus cycle op addr 1 data 2 op addr 1 data 2 read read array 1 write dna 0xff C C C read device identifier 2 write dna 0x90 read dba + ia id read cfi 2 write dna 0x98 read dba + cfi-a cfi-d read status register 2 write dna 0x70 read dna srd clear status register 1 write dna 0x50 C C C program word program 2 write wa 0x40 write wa wd buffered program 3 >2 write wa 0xe8 write wa n - 1 buffered enhanced factory program (befp) 4 >2 write wa 0x80 write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write dna 0xb0 C C C program/erase resume 1 write dna 0xd0 C C C protection block lock 2 write ba 0x60 write ba 0x01 block unlock 2 write ba 0x60 write ba 0xd0 block lock down 2 write ba 0x60 write ba 0x2f program otp register 2 write pra 0xc0 write otp-ra otp-d program lock register 2 write lra 0xc0 write lra lrd configuration configure read configuration register 2 write rcd 0x60 write rcd 0x03 blank check block blank check 2 write ba 0xbc write ba d0 efi extended function interface 5 >2 write wa 0xeb write wa sub-op code notes: 1. first command cycle address should be the same as the operations target address. dba = device base address (needed for dual die 512mb device); dna = address within the de- vice; ia = identification code address offset; cfi-a = read cfi address offset; wa = word address of memory location to be written; ba = address within the block; otp-ra = pro- tection register address; lra = lock register address; rcd = read configuration register data on a[16:1] for easy bga and tsop, a[15:0] for quad+ package. 2. id = identifier data; cfi-d = cfi data on dq[15:0]; srd = status register data; wd = word data; n = word count of data to be loaded into the write buffer; otp-d = protection register data; lrd = lock register data. 256mb and 512mb (256mb/256mb), p30-65nm device command bus cycles pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 512 words of data. then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data. 5. the second cycle is a sub-op-code, the data written on third cycle is n-1; 1 n 512. the subsequent cycles load data words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the final cycle is the con- firm cycle 0xd0). 256mb and 512mb (256mb/256mb), p30-65nm device command bus cycles pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read operations the device supports two read modes: asynchronous page mode and synchronous burst mode. asynchronous page mode is the default read mode after device power-up or a re- set. under asynchronous page mode, the device can also perform single word read. the read configuration register must be configured to enable synchronous burst reads of the array. the device can be in any of four read states: read array, read identifier, read status, or read cfi. upon power-up, or after a reset, the device defaults to read array. to change the read state, the appropriate read command must be written to the device. asynchronous page mode read following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to read array. however, to perform array reads after any other device operation (write operation), the read array command must be issued in or- der to read from the array. asynchronous page mode reads can only be performed when read configuration regis- ter bit rcr15 is set. to perform an asynchronous page-mode read, an address is driven onto the address bus, and ce# and adv# are asserted. we# and rst# must already have been de-asser- ted. wait is de-asserted during asynchronous page mode. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. clk is not used for asynchronous page mode reads, and is ignored. if only asynchronous reads are to be performed, clk should be tied to a valid v ih or v ss level, wait signal can be floated, and adv# must be tied to ground. array data is driven onto dq[15:0] after an initial ac- cess time t avqv delay. in asynchronous page mode, 16 data words are sensed simultaneously from the array and loaded into an internal page buffer. the buffer word corresponding to the initial address on the address bus is driven onto dq[15:0] after the initial access delay. the lowest four address bits determine which word of the 16-word page is output from the data buffer at any given time. note: asynchronous page read mode is only supported in main array. asynchronous single word read to perform an asynchronous single word read, an address is driven onto the address bus, and ce# is asserted. adv# can either be driven high to latch the address or be held low throughout the read cycle. we# and rst# must already have been de-asser- ted. wait is set to a de-asserted state during single word mode, as determined by bit 10 of the read configuration register. clk is not used for asynchronous single word reads, and is ignored. if asynchronous reads are to be performed only, clk should be tied to a valid v ih or v ss level, wait can be floated, and adv# must be tied to ground. after oe# is asserted, the data is driven onto dq[15:0] after an initial access time t avqv or t glqv delay. 256mb and 512mb (256mb/256mb), p30-65nm read operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
synchronous burst mode read read configuration register bits rcr[15:0] must be set before synchronous burst opera- tion can be performed. synchronous burst mode can be performed for both array and non-array reads such as read id, read status, or read query. to perform a synchronous burst read, an initial address is driven onto the address bus, and ce# and adv# are asserted. we# and rst# must already have been de-asserted. adv# is asserted, and then de-asserted to latch the address. alternately, adv# can re- main asserted throughout the burst access, in which case the address is latched on the next valid clk edge while adv# is asserted. during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid clk edge after the initial access latency delay. subsequent data is output on valid clk edges following a minimum delay. however, for a synchro- nous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. refer to the timing diagrams for more detailed information. read cfi the read cfi command instructs the device to output cfi data when read. see com- mon flash interface for details on issuing the read cfi command, and for details on addresses and offsets within the cfi database. read device id the read device identifier command instructs the device to output manufacturer code, device identifier code, block lock status, protection register data, or configuration register data. table 12: device id information item address data manufacturer code 0x00 0x89 device id code 0x01 id (see the device id codes table ) block lock configuration block is unlocked block is locked block is not locked down block is locked down block base address + 0x02 lock bit dq 0 = 0b0 dq 0 = 0b1 dq 1 = 0b0 dq 1 = 0b1 read configuration register 0x05 rcr contents general purpose register device base address + 0x07 general purpose register data lock register 0 0x80 pr-lk0 data 64-bit factory-programmed otp register 0x81C0x84 factory otp register data 64-bit user-programmable otp register 0x85C0x88 user otp register data lock register 1 0x89 pr-lk1 otp register lock data 128-bit user-programmable protection regis- ters 0x8aC0x109 otp register data 256mb and 512mb (256mb/256mb), p30-65nm read operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device id codes table 13: device id codes id code type device density device identifier codes Ct (top parameter) Cb (bottom parameter) device code 256mb 8919 891c note: 1. the 512mb devices do not have a unique device id associated with them. each die with- in the stack can be identified by device id codes. 256mb and 512mb (256mb/256mb), p30-65nm device id codes pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program operations successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be de-asserted and the block must be unlocked before at- tempting to program the block. attempting to program a locked block causes a program error (sr4 and sr1 set) and termination of the operation. see security modes for details on locking and unlocking blocks. word programming (40h) word programming operations are initiated by writing the word program setup command to the device (see the command codes and definitions table). this is fol- lowed by a second write to the device with the address and data to be programmed. the device outputs status register data when read (see the word program flowchart). v pp must be above v pplk , and within the specified v ppl min/max values. during programming, the device executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. programming the array changes 1s to 0s. memory array bits that are 0s can be changed to 1s only by erasing the block (see erase operations). the status register can be examined for programming progress and errors by reading at any address. the device remains in the read status register state until another com- mand is written to the device. sr7 indicates the programming status while the sequence executes. commands that can be issued to the device during programming are program suspend, read sta- tus register, read device identifier, read cfi, and read array (this returns unknown data). when programming has finished, sr4 (when set) indicates a programming failure. if sr3 is set, the device could not perform the word programming operation because v pp was outside of its acceptable limits. if sr1 is set, the word programming opera- tion attempted to program a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed. buffered programming (e8h, d0h) the device features a 512-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buf- fer data is programmed into the array in buffer-size increments. this can improve sys- tem programming performance significantly over non-buffered programming. when the buffered programming setup command is issued, status register in- formation is updated and reflects the availability of the buffer. sr7 indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. note: the device default state is to output sr data after the buffered program- ming setup command. ce# and oe# low drive device to update status register. it is not allowed to issue 70h to read sr data after e8h command; otherwise, 70h would be counted as word count. 256mb and 512mb (256mb/256mb), p30-65nm program operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional device addresses and da- ta. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 512-word boundary (a[9:1] = 0x00 for easy bga and tsop, a[8:0] for quad+ package; see part numbering information). the maximum buffer size would be 256-word if the misaligned address range is crossing a 512-word boundary during programming. after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the device begins to program buffer contents to the array. if a command other than the buffered programming confirm command is written to the device, a command sequence error occurs and sr[7,5,4] are set. if an error occurs while writing to the array, the device stops program- ming, and sr[7,4] are set, indicating a programming failure. when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming setup command and repeating the buffered program sequence. buffered programming may be performed with v pp = v ppl or v pph (see operating conditions for limitations when operating the device with v pp = v pph ). if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command se- quence error, and sr[5,4] are set. if buffered programming is attempted while v pp is at or below v pplk , sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. buffered enhanced factory programming (80h, d0h) buffered enhanced factory programming (befp) speeds up multilevel cell (mlc) pro- gramming. the enhanced programming algorithm used in befp eliminates traditional programming elements that drive up overhead in device programmer systems. befp consists of three phases: setup, program/verify, and exit (see the befp flowchart). it uses a write buffer to spread mlc program performance across 512 data words. verifi- cation occurs in the same phase as programming to accurately program the cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this en- hancement eliminates three write cycles per buffer: two commands and the word count for each set of 512 data words. host programmer bus cycles fill the device write buffer followed by a status check. sr0 indicates when data from the buffer has been program- med into sequential array locations. following the buffer-to-flash array programming sequence, the device increments in- ternal addressing to automatically select the next 512-word array boundary. this aspect of befp saves host programming equipment the address bus setup overhead. 256mb and 512mb (256mb/256mb), p30-65nm program operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
with adequate continuity testing, programming equipment can rely on the devices in- ternal verification to ensure that the device has programmed properly. this eliminates the external post-program verification and its associated overhead. table 14: befp requirements parameter/issue requirement notes case temperature t c = 30c 10c v cc nominal v cc v pp driven to v pph setup and confirm target block must be unlocked before issuing the befp setup and confirm commands. programming the first-word address (wa0) of the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. buffer alignment wa0 must align with the start of an array buffer boundary. 1 note: 1. word buffer boundaries in the array are determined by the lowest 9 address bits (0x000 through 0x1ff). the alignment start point is 0x000. table 15: befp considerations parameter/issue requirement notes cycling for optimum performance, cycling must be limited below 50 erase cycles per block. 1 programming blocks befp programs one block at a time; all buffer data must fall within a single block. 2 suspend befp cannot be suspended. programming the ar- ray programming to the array can occur only when the buffer is full. 3 notes: 1. some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 2. if the internal address counter increments beyond the block's maximum address, ad- dressing wraps around to the beginning of the block. 3. if the number of words is less than 512, remaining locations must be filled with 0xffff. befp setup phase: after receiving the befp setup and confirm command se- quence, sr7 (ready) is cleared, indicating that the device is busy with befp algorithm startup. a delay before checking sr7 is required to allow the device enough time to per- form all of its setups and checks (block lock status, v pp level, etc.). if an error is detected, sr4 is set and befp operation terminates. if the block was found to be locked, sr1 is also set. sr3 is set if the error occurred due to an incorrect v pp level. note: reading from the device after the befp setup and confirm command se- quence outputs status register data. do not issue the read status register com- mand; it will be interpreted as data to be loaded into the buffer. befp program/verify phase: after the befp setup phase has completed, the host pro- gramming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr7 cleared indicates the device is busy and the befp program/veri- fy phase is activated. sr0 indicates the write buffer is available. two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. for befp, the count value for buffer loading is always 256mb and 512mb (256mb/256mb), p30-65nm program operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
the maximum buffer size of 512 words. during the buffer-loading sequence, data is stor- ed to sequential buffer locations starting at address 0x00. programming of the buffer contents to the array starts as soon as the buffer is full. if the number of words is less than 512, the remaining buffer locations must be filled with 0xffff. note: the buffer must be completely filled for programming to occur. supplying an ad- dress outside of the current block's range during a buffer-fill sequence causes the algo- rithm to exit immediately. any data previously loaded into the buffer during the fill cy- cle is not programmed into the array. the starting address for data entry must be buffer size aligned; if not, the befp algo- rithm will be aborted, the program fails, and the (sr4) flag will be set. data words from the write buffer are directed to sequential memory locations in the ar- ray; programming continues from where the previous buffer sequence ended. the host programming system must poll sr0 to determine when the buffer program sequence completes. sr0 cleared indicates that all buffer data has been transferred to the array; sr0 set indicates that the buffer is not available yet for the next fill cycle. the host sys- tem may check full status for errors at any time, but it is only necessary on a block basis after befp exit. after the buffer fill cycle, no write cycles should be issued to the de- vice until sr0 = 0 and the device is ready for the next buffer fill. note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. the host programming system continues the befp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current blocks range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the de- vice enters the befp exit phase. program suspend issuing the program suspend command while programming suspends the pro- gramming operation. this allows data to be accessed from the device other than the one being programmed. the program suspend command can be issued to any de- vice address. a program operation can be suspended to perform reads only. addition- ally, a program operation that is running during an erase suspend can be suspended to perform a read operation. when a programming operation is executing, issuing the program suspend com- mand requests the device to suspend the programming algorithm at predetermined points. the device continues to output status register data after the program sus- pend command is issued. programming is suspended when sr[7,2] are set. to read data from the device, the read array command must be issued. read array, read status register, read device identifier, read cfi, and program re- sume valid commands during a program suspend. during a program suspend, de-asserting ce# places the device in standby, reducing ac- tive current. v pp must remain at its programming level, and wp# must remain un- changed while in program suspend. if rst# is asserted, the device is reset. 256mb and 512mb (256mb/256mb), p30-65nm program operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program resume the resume command instructs the device to continue programming, and automati- cally clears sr[7,2]. this command can be written to any address. if error bits are set, the status register should be cleared before issuing the next command. rst# must re- main de-asserted. program protection when v pp = v il , absolute hardware write protection is provided for all device blocks. if v pp is at or below v pplk , programming operations halt and sr3 is set, indicating a v pp - level error. block lock registers are not affected by the voltage level on v pp ; they may still be programmed and read, even if v pp is less than v pplk . figure 11: example v pp supply connections v cc v pp v cc v pp 10k < -factory programming with v pp = v pph -complete with program/erase protection when v < pp v pplk v cc v cc v pp -low voltage programming only -full device protection unavailable -low voltage programming only -logic control of device protection v cc prot# v cc v pp -low voltage and factory programming v cc v pp v cc v pp v pph = 256mb and 512mb (256mb/256mb), p30-65nm program operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
erase operations block erase command erase operations are performed on a block basis. an entire block is erased each time a block erase command sequence is issued, and only one block is erased at a time. when a block is erased, each bit within that block reads as a logical 1. a block erase operation is initiated by writing the block erase setup command to the address of the block to be erased, followed by the block erase confirm com- mand. if the device is placed in standby (ce# de-asserted) during a block erase oper- ation, the device completes the operation before entering standby. the v pp value must be above v pplk and the block must be unlocked. during a block erase operation, the device executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. erasing the array changes the value in each cell from a 1 to a 0. memory block array cells that with a value of 1 can be changed to 0 only by programming the block. the status register can be examined for block erase progress and errors by reading any address. the device remains in the read status register state until another command is written. sr0 indicates whether the addressed block is erasing. sr7 is set upon erase completion. sr7 indicates block erase status while the sequence executes. when the block erase operation has completed, sr5 = 1 (set) indicates an erase failure. sr3 = 1 indicates that the device could not perform the block erase operation because v pp was outside of its acceptable limits. sr1 = 1 indicates that the block erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow after the block erase operation has completed. the block erase operation is aborted by performing a reset or powering down the device. in either case, data integrity cannot be ensured, and it is recommended to erase again the blocks aborted. blank check command the blank check operation determines whether a specified main block is blank; that is, completely erased. other than a blank check operation, only a block erase op- eration can ensure a block is completely erased. blank check is especially useful when a block erase operation is interrupted by a power loss event. a blank check operation can apply to only one block at a time. the only operation allowed simultaneously is a read status register operation. suspend and re- sume operations and a blank check operation are mutually exclusive. a blank check operation is initiated by writing the blank check setup command to the block address, followed by the check confirm command. when a successful command sequence is entered, the device automatically enters the read status state. the device then reads the entire specified block and determines whether any bit in the block is programmed or over-erased. 256mb and 512mb (256mb/256mb), p30-65nm erase operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
blank check operation progress and errors are determined by reading the status reg- ister at any address within the block being accessed. sr7 = 0 is a blank check busy status. sr7 = 1 is a blank check operation complete status. the status register should be checked for any errors and then cleared. if the blank check operation fails, mean- ing the block is not completely erased, sr5 = 1. ce# or oe# toggle (during polling) up- dates the status register. the read status register command must always be followed by a clear status register command. the device remains in status register mode until another com- mand is written to the device. any command can follow once the blank check com- mand is complete. erase suspend command the erase suspend command suspends a block erase operation that is in pro- gress, enabling access to data in memory locations other than the one being erased. the erase suspend command can be issued to any device address. a block erase oper- ation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended. when a block erase operation is executing, issuing the erase suspend command requests the device to suspend the erase algorithm at predetermined points. the device continues to output status register data after the erase suspend command is issued. block erase is suspended when sr[7,6] are set. to read data from the device (other than an erase-suspended block), the read array command must be issued. during erase suspend, a program command can be issued to any block other than the erase-suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read sta- tus register, read device identifier, read cfi, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock down are valid commands during an erase suspend operation. during an erase suspend, de-asserting ce# places the device in standby, reducing active current. v pp must remain at a valid level, and wp# must remain unchanged while in erase suspend. if rst# is asserted, the device is reset. erase resume command the erase resume command instructs the device to continue erasing, and automati- cally clears sr[7,6]. this command can be written to any address. if status register error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain de-asserted. erase protection when v pp = v il , absolute hardware erase protection is provided for all device blocks. if v pp is at or below v pplk , erase operations halt and sr3 is set indicating a v pp -level er- ror. 256mb and 512mb (256mb/256mb), p30-65nm erase operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
security operations block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power-up in a locked state to protect array data from be- ing altered during power transitions. any block can be locked or unlocked with no la- tency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented using the block lock and block un- lock commands. hardware-controlled security can be implemented using the block lock down command along with asserting wp#. also, v pp data security can be used to inhibit program and erase operations. block lock command to lock a block, issue the block lock setup command, followed by the block lock command issued to the desired blocks address. if the set read configuration register command is issued after the block lock setup command, the device configures the rcr instead. block lock and unlock operations are not affected by the voltage level on v pp . the block lock bits may be modified and/or read even if v pp is at or below v pplk . block unlock command the block unlock command is used to unlock blocks. unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the device is reset or powered down. if a block is in a lock-down state, wp# must be de-asserted be- fore it can be unlocked. block lock down command a locked or unlocked block can be locked-down by writing the block lock down command sequence. blocks in a lock-down state cannot be programmed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can only be unlocked by issuing the block unlock command with wp# de-asserted. to return an unlocked block to locked-down state, a block lock down command must be issued prior to changing wp# to v il . locked-down blocks revert to the locked state upon reset or power up the device. block lock status the read device identifier command is used to determine a blocks lock status. dq[1:0] display the addressed blocks lock status; dq0 is the addressed blocks lock bit, while dq1 is the addressed blocks lock-down bit. 256mb and 512mb (256mb/256mb), p30-65nm security operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 12: block locking state diagram [000] program/erase allowed wp# = v il = 0 wp# = v il = 0 program/erase prevented (virtual lock-down) program/erase prevented wp# = v ih = 1 [110] [100] [001] [011] [111] [101] [010] (locked down) 2fh 2fh 2fh 2fh 01h d0h 01h/2fh 01h d0h d0h d0h, 01h, or 2fh (power-up/ reset default) (lock down disabled, wp# = v ih ) (power-up/ reset default) wp# toggle wp# toggle program/erase allowed wp# = v ih = 1 note: 1. d0h = unlock command; 01h = lock command; 60h (not shown) lock setup com- mand; 2fh = lock down command. block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr7 and sr6 are set, indicating the device is suspended and ready to accept another command. next, write the desired lock command sequence to a block, which changes the lock state of that block. after completing block lock or block unlock operations, re- sume the erase operation using the erase resume command. note: a block lock setup command followed by any command other than block lock, block unlock, or block lock down produces a command sequence error and set sr4 and sr5. if a command sequence error occurs during an erase suspend, sr4 and sr5 remains set, even after the erase operation is resumed. unless the status register is cleared using the clear status register command before resuming the erase op- eration, possible erase errors may be masked by the command sequence error. if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is re- sumed. block lock operations cannot occur during a program suspend. 256mb and 512mb (256mb/256mb), p30-65nm security operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
selectable otp blocks the otp security feature on the device is backward-compatible to the earlier genera- tion devices. contact your local micron representative for details about its implementa- tion. password access the password access is a security enhancement offered on the device. this feature pro- tects information stored in array blocks by preventing content alteration or reads until a valid 64-bit password is received. the password access may be combined with nonvola- tile protection and/or volatile protection to create a multi-tiered solution. contact your micron sales office for further details concerning password access. 256mb and 512mb (256mb/256mb), p30-65nm security operations pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
status register read status register to read the status register, issue the read status register command at any address. status register information is available at the address that the read status register, word program, or block erase command is issued to. status register data is auto- matically made available following a word program, block erase, or block lock com- mand sequence. reads from the device after any of these command sequences will out- put the devices status until another valid command is written (e.g. read array com- mand). the status register is read using single asynchronous mode or synchronous burst mode reads. status register data is output on dq[7:0], while 0x00 is output on dq[15:8]. in asynchronous mode, the falling edge of oe# or ce# (whichever occurs first) updates and latches the status register contents. however, when reading the status register in synchronous burst mode, ce# or adv# must be toggled to update status data. the device write status bit (sr7) provides the overall status of the device. sr[6:1] present status and error information about the program, erase, suspend, v pp , and block lock operations. note: reading the status register is a nonarray read operation. when the operation oc- curs in asynchronous page mode, only the first data is valid and all subsequent data are undefined. when the operation occurs in synchronous burst mode, the same data word requested will be output on successive clock edges until the burst length requirements are satisfied. table 16: status register description notes apply to entire table bits name bit settings description 7 device write status (dws) 0 = busy 1 = ready status bit: indicates whether a program or erase command cycle is in progress. 6 erase suspend status (ess) 0 = not in effect 1 = in effect status bit: indicates whether an erase operation has been or is going to be suspended. 5:4 erase/blank check status (es) program status (ps) 00 = program/erase successful 01 = program error 10 = erase/blank check error 11 = command sequence error status/error bit: indicates whether an erase/ blank check or program operation was success- ful. when an error is returned, the operation is aborted. 3 v pp status (vpps) 0 = within limits 1 = exceeded limits (v pp v pplk ) status bit: indicates whether a program/erase operation is within acceptable voltage range limits. 2 program suspend status (pss) 0 = not in effect 1 = in effect status bit: indicates whether a program opera- tion has been or is going to be suspended. 1 block lock status (bls) 0 = not locked 1 = locked (operation aborted) status bit: indicates whether a block is locked when a program or erase operation is initiated. 0 befp status (bws) 0 = befp complete 1 = befp in progress status bit: indicates whether befp data has com- pleted loading into the buffer. notes: 1. default value = 0x80. 2. always clear the status register prior to resuming erase operations. this eliminates sta- tus register ambiguity when issuing commands during erase suspend. if a command 256mb and 512mb (256mb/256mb), p30-65nm status register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
sequence error occurs during an erase suspend, the status register contains the com- mand sequence error status (sr[7,5,4] set). when the erase operation resumes and fin- ishes, possible errors during the operation cannot be detected via the status register be- cause it contains the previous error status. 3. when bits 5:4 indicate a program/erase operation error, either a clear status reg- ister 50h) or a reset command must be issued with a 15s delay. clear status register the clear status register command clears the status register. it functions inde- pendently of v pp . the device sets and clears sr[7,6,2], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command se- quence to avoid any ambiguity. a device reset also clears the status register. 256mb and 512mb (256mb/256mb), p30-65nm status register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
configuration register read configuration register the read configuration register (rcr) is a 16-bit read/write register used to select bus read mode (synchronous or asynchronous) and to configure device synchronous burst read characteristics. to modify rcr settings, use the configure read configura- tion register command. rcr contents can be examined using the read device identifier command and then reading from offset 0x05. on power-up or exit from re- set, the rcr defaults to asynchronous mode. rcr bits are described in more detail be- low. note: reading the configuration register is a nonarray read operation. when the oper- ation occurs in asynchronous page mode, only the first data is valid, and all subsequent data are undefined. when the operation occurs in synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. table 17: read configuration register bits name settings/description 15 read mode (rm) 0 = synchronous burst mode read 1 = asynchronous page mode read (default) 14:11 latency count (lc[3:0]) 0000 = code 0 (reserved) 0001 = code 1 (reserved) 0010 = code 2 0011 = code 3 0100 = code 4 0101 = code 5 0110 = code 6 0111 = code 7 1000 = code 8 1001 = code 9 1010 = code 10 1011 = code11 1100 = code 12 1101 = code 13 1110 = code 14 1111 = code 15 (default) 10 wait polarity (wp) 0 = wait signal is active low (default) 1 = wait signal is active high 9 reserved (r) default 0, nonchangeable 8 wait delay (wd) 0 = wait de-asserted with valid data 1 = wait de-asserted one data cycle before valid data (default) 7 burst sequence (bs) default 0, nonchangeable 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) default 0, nonchangeable 3 burst wrap (bw) 0 = wrap; burst accesses wrap within burst length set by bl[2:0] 1 = no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 = 4-word burst 010 = 8-word burst 011 = 16-word burst 111 = continuous burst (default) (other bit settings are reserved) read mode the read mode (rm) bit selects synchronous burst mode or asynchronous page mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
latency count the latency count (lc) bits tell the device how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first valid data word is driven to dq[15:0]. the input clock frequency is used to deter- mine this value. the first access latency count figure shows the data output latency for different lc settings. figure 13: first access latency count code 1 ( reserved ) code 6 code 5 code 4 code 3 code 2 code 0 ( reserved ) code 7 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] clk [c] note: 1. first access latency count calculation: ? 1 / clk frequency = clk period (ns) ? n x (clk period) t avqv (ns) C t chqv (ns) ? latency count = n 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 14: example latency count setting using code 3 clk ce# adv# a[max:1] d[15:0] t data 0 1 2 3 4 high-z code 3 address r103 data end of wordline considerations end of wordline (eowl) wait states can result when the starting address of the burst op- eration is not aligned to a 16-word boundary; that is, a[4:1] of the start address does not equal 0x0. the figure below illustrates the end of wordline wait state(s) that occur after the first 16-word boundary is reached. the number of data words and wait states is summarized in the table below. figure 15: end of wordline timing diagram clk adv# eowl data oe# wait# a[max:1] dq[15:0] latency count data data address 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 18: end of wordline data and wait state comparison latency count 130nm 65nm data words wait states data words wait states 1 not supported not supported not supported not supported 2 4 0 to 1 16 0 to 1 3 4 0 to 2 16 0 to 2 4 4 0 to 3 16 0 to 3 5 4 0 to 4 16 0 to 4 6 4 0 to 5 16 0 to 5 7 4 0 to 6 16 0 to 6 8 not supported not supported 16 0 to 7 9 16 0 to 8 10 16 0 to 9 11 16 0 to 10 12 16 0 to 11 13 16 0 to 12 14 16 0 to 13 15 16 0 to 14 wait signal polarity and functionality the wait polarity (wp) bit, rcr10 determines the asserted level (v oh or v ol ) of wait. when wp is set, wait is asserted high (default). when wp is cleared, wait is asserted low. the wait signal changes state on valid clock edges during active bus cycles (ce# asserted, oe# asserted, rst# de-asserted). the wait signal indicates data valid when the device is operating in synchronous mode (rcr15 = 0). the wait signal is only de-asserted when data is valid on the bus. when the device is operating in synchronous nonarray read mode, such as read status, read id, or read cfi, the wait signal is also de-asserted when data is valid on the bus. wait behavior during synchronous nonarray reads at the end of wordline works correctly on- ly on the first data access. when the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, wait is set to a de-as- serted state as determined by rcr10. table 19: wait functionality table condition wait notes ce# = 1, oe# = x or ce# = 0, oe# = 1 high-z 1 ce# = 0, oe# = 0 active 1 synchronous array reads active 1 synchronous nonarray reads active 1 all asynchronous reads de-asserted 1 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 19: wait functionality table (continued) condition wait notes all writes high-z 1, 2 notes: 1. active means that wait is asserted until data becomes valid, then deasserts. 2. when oe# = v ih during writes, wait = high-z. wait delay the wait delay (wd) bit controls the wait assertion delay behavior during synchro- nous burst reads. wait can be asserted either during or one data cycle before valid data is output on dq[15:0]. when wd is set, wait is de-asserted one data cycle before valid data (default). when wd is cleared, wait is de-asserted during valid data. burst sequence the burst sequence (bs) bit selects linear burst sequence (default). only linear burst se- quence is supported. the synchronous burst sequence for all burst lengths, as well as the effect of the burst wrap (bw) setting are shown below. table 20: burst sequence word ordering start address (dec) burst wrap (rcr3) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-414-15 0-1-2-3-4-5-6- 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-515-0 1-2-3-4-5-6-7- 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-615-0-1 2-3-4-5-6-7-8- 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-715-0-1-2 3-4-5-6-7-8-9- 4 0 4-5-6-7-0-1-2-3 4-5-6-7-815-0-1-2-3 4-5-6-7-8-9-10 5 0 5-6-7-0-1-2-3-4 5-6-7-8-915-0-1-2-3-4 5-6-7-8-9-10-11 6 0 6-7-0-1-2-3-4-5 6-7-8-9-1015-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 0 7-0-1-2-3-4-5-6 7-8-9-1015-0-1-2-3-4-5-6 7-8-9-10-11-12-13 ? ? ? ? ? ? 14 0 14-15-0-1-212-13 14-15-16-17-18-19-20- 15 0 15-0-1-2-313-14 15-16-17-18-19-20-21- ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-414-15 0-1-2-3-4-5-6- 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-515-16 1-2-3-4-5-6-7- 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-616-17 2-3-4-5-6-7-8- 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-717-18 3-4-5-6-7-8-9- 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 20: burst sequence word ordering (continued) start address (dec) burst wrap (rcr3) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 4 1 4-5-6-7-8-9-10-11 4-5-6-7-818-19 4-5-6-7-8-9-10 5 1 5-6-7-8-9-10-11-12 5-6-7-8-919-20 5-6-7-8-9-10-11 6 1 6-7-8-9-10-11-12-13 6-7-8-9-1020-21 6-7-8-9-10-11-12- 7 1 7-8-9-10-11-12-13-14 7-8-9-10-1121-22 7-8-9-10-11-12-13 ? ? ? ? ? ? 14 1 14-15-16-17-1828-29 14-15-16-17-18-19-20- 15 1 15-16-17-18-1929-30 15-16-17-18-19-20-21- clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for clk. this clock edge is used at the start of a burst cycle to output synchronous data and to assert/de-assert wait. burst wrap the burst wrap (bw) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word length boundaries or cross word length boun- daries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. when performing synchronous burst reads with bw set (no wrap), an output delay may occur when the burst sequence crosses its first device row (16-word) boundary. if the burst sequences start address is 4-word aligned, then no delay occurs. if the start ad- dress is at the end of a 4-word boundary, the worst-case output delay is one clock cycle less than the first access latency count. this delay can take place only once and doesnt occur if the burst sequence does not cross a device row boundary. wait informs the system of this delay when it occurs. burst length the burst length bits (bl[2:0]) select the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 4-word, 8-word, 16-word, or con- tinuous. continuous burst accesses are linear only and do not wrap within any word length boundaries. when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the burstable address space. 256mb and 512mb (256mb/256mb), p30-65nm configuration register pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
one-time programmable registers read otp registers the device contains 17 otp registers that can be used to implement system security measures and/or device identification. each otp register can be individually locked. the first 128-bit otp register is comprised of two 64-bit (8-word) segments. the lower 64-bit segment is preprogrammed at the micron factory with a unique 64-bit number. the upper 64-bit segment, as well as the other sixteen 128-bit otp registers, are blank. users can program them as needed. once programmed, users can also lock the otp register(s) to prevent additional bit programming (see the otp register map figure be- low). the otp registers contain otp bits; when programmed, pr bits cannot be erased. each otp register can be accessed multiple times to program individual bits, as long as the register remains unlocked. each otp register has an associated lock register bit. when a lock register bit is pro- grammed, the associated otp register can only be read; it can no longer be program- med. additionally, because the lock register bits themselves are otp, when program- med, they cannot be erased. therefore, when an otp register is locked, it cannot be un- locked. the otp registers can be read from an otp-ra address. to read the otp register, a read device identifier command is issued at an otp-ra address to place the de- vice in the read device identifier state. next, a read operation is performed using the address offset corresponding to the register to be read. the device identifier informa- tion table shows the address offsets of the otp registers and lock registers. pr data is read 16 bits at a time. 256mb and 512mb (256mb/256mb), p30-65nm one-time programmable registers pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 16: otp register map 0 x 8 9 lock register 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 x 10 2 0 x 10 9 0 x 8 a 0 x 9 1 0 x 8 8 0 x 8 5 64-bit segment 64-bit segment lock register 0 register 0 128-bit otp register 1 128-bit otp 0 x 8 4 0 x 8 1 0 x 8 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 register 16 128-bit otp factory programed user programmable user programmable user programmable program otp registers to program an otp register, a program otp register command is issued at the pa- rameters base address plus the offset of the desired otp register location. next, the de- sired otp register data is written to the same otp register address. the device programs the 64-bit and 128-bit user-programmable otp register data 16 bits at a time. issuing the program otp register command outside of the otp reg- isters address space causes a program error (sr4 set). attempting to program a locked otp register causes a program error (sr4 set) and a lock error (sr1 set). lock otp registers each otp register can be locked by programming its respective lock bit in the lock regis- ter. the corresponding bit in the lock register is programmed by issuing the program lock register command, followed by the desired lock register data. the physical ad- dresses of the lock registers are 0x80 for register 0 and 0x89 for register 1; these address- es are used when programming the lock registers. bit 0 of lock register 0 is programmed during the manufacturing process, locking the lower-half segment of the first 128-bit otp register. bit 1 of lock register 0, which corre- sponds to the upper-half segment of the first 128-bit otp register, can be programmed by the user . when programming bit 1 of lock register 0, all other bits need to be left as 1 such that the data programmed is 0xfffd. 256mb and 512mb (256mb/256mb), p30-65nm one-time programmable registers pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
lock register 1 controls the the upper sixteen 128-bit otp registers. each bit of lock reg- ister 1 corresponds to a specific 128-bit otp register. programming a bit in lock register 1 locks the corresponding 128-bit otp register; e.g., programming lr1.0 locks the corre- sponding otp register 1. note: once locked, the otp registers cannot be unlocked. 256mb and 512mb (256mb/256mb), p30-65nm one-time programmable registers pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
common flash interface the cfi is part of an overall specification for multiple command-set and control-inter- face descriptions. system software can parse the cfi database structure to obtain infor- mation about the device, such as block size, density, bus width, and electrical specifica- tions. the system software determines which command set to use to properly perform a write command, a block erase or read command, and to otherwise control the device. information in the cfi database can be viewed by issuing the read cfi com- mand. read cfi structure output the read cfi command obtains cfi database structure information and always out- puts it on the lower byte, dq[7:0], for a word-wide (x16) device. this cfi-compliant de- vice always outputs 00h data on the upper byte (dq[15:8]). the numerical offset value is the address relative to the maximum bus width the device supports. for this device family, the starting address is a 10h, which is a word address for x16 devices. for example, at this starting address of 10h, a read cfi command out- puts an ascii q in the lower byte and 00h in the higher byte as shown here. in all the cfi tables shown here, address and data are represented in hexadecimal nota- tion. in addition, because the upper byte of word-wide devices is always 00h, as shown in the example here, the leading 00 has been dropped and only the lower byte value is shown. following is a table showing the cfi output for a x16 device, beginning at ad- dress 10h and a table showing an overview of the cfi database sections with their ad- dresses. table 21: example of cfi output (x16 device) as a function of device and mode device hex offset hex code ascii value (dq[15:8]) ascii value (dq[7:0]) address 00010: 51 00 q 00011: 52 00 r 00012: 59 00 y 00013: p_id lo 00 primary vendor id 00014: p_id hi 00 00015: p lo 00 primary vendor table address 00016: p hi 00 00017: a_id lo 00 alternate vendor id 00018: a_id hi 00 : : : : : : : : 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 22: cfi database: addresses and sections address section name description 00001:fh reserved reserved for vendor-specific information 00010h cfi id string flash device command set id (identification) and vendor da- ta offset 0001bh system interface information flash device timing and voltage 00027h device geometry definition flash device layout p primary micron-specific extended query vendor-defined informaton specific to the primary vendor algorithm (offset 15 defines p which points to the primary micron-specific extended query table.) table 23: cfi id string hex offset length description address hex code ascii value (dq[7:0]) 10h 3 query unique ascii string qry 10: - -51 q 11: - -52 r 12: - -59 y 13h 2 primary vendor command set and control interface id code. 16-bit id code for ven- dor-specified algorithms. 13: - -01 primary vendor id number 14: - -00 15h 2 extended query table primary algorithm address. 15: - -0a primary vendor table ad- dress, primary algorithm 16: - -01 17h 2 alternate vendor command set and control interface id code. 0000h means no second vendor-specified algorithm exists. 17: - -00 alternate vendor id number 18: - -00 19h 2 secondary algorithm extended query table address. 0000h means none exists. 19: - -00 primary vendor table ad- dress, secondary algorithm 1a: - -00 note: 1. the cfi id string provides verification that the device supports the cfi specification. it also indicates the specification version and supported vendor-specific command sets. 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 24: system interface information hex offset length description address hex code ascii value (dq[7:0]) 1bh 1 v cc logic supply minimum program/erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 bcd volts 1bh - -17 1.7v 1ch 1 v cc logic supply maximum program/erase volt- age. bits 0 - 3 bcd 100 mv bits 4 - 7 bcd volts 1ch - -20 2.0v 1dh 1 v pp [programming] supply minimum program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex volts 1dh - -85 8.5v 1eh 1 v pp [programming] supply maximum program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex volts 1eh - -95 9.5v 1fh 1 n such that typical single word program time- out = 2 n s. 1fh - -09 512s 20h 1 n such that typical full buffer write timeout = 2 n s. 20h - -0a 1024s 21h 1 n such that typical block erase timeout = 2 n ms. 21h - -0a 1s 22h 1 n such that typical full chip erase timeout = 2 n ms. 22h - -00 na 23h 1 n such that maximum word program timeout = 2 n times typical. 23h - -01 1024s 24h 1 n such that maximum buffer write timeout = 2 n times typical. 24h - -02 4096s 25h 1 n such that maximum block erase timeout = 2 n times typical. 25h - -02 4s 26h 1 n such that maximum chip erase timeout = 2 n times typical. 26h - -00 na 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 25: device geometry hex offset length description address hex code ascii value (dq[7:0]) 27h 1 n such that device size in bytes = 2 n . 27: see note 1 28h 2 flash device interface code assignment: n such that n + 1 specifies the bit field that represents the flash device width capabilities as described here: bit 0: x8 bit 1: x16 bit 2: x32 bit 3: x64 bits 4 - 7: C bits 8 - 15: C 28: - -01 x16 29: - -00 2ah 2 n such that maximum number of bytes in write buffer = 2 n . 2ah - -0a 1024 2bh - -00 2ch 1 number of erase block regions (x) within the device: 1) x = 0 means no erase blocking; the device erases in bulk. 2) x specifies the number of device regions with one or more contiguous, same-size erase blocks. 3) symmetrically blocked partitions have one blocking region. 2ch see note 1 2dh 4 erase block region 1 information: bits 0 - 15 = y, y + 1 = number of identical-size erase blocks. bits 16 - 31 = z, region erase block(s) size are z x 256 bytes. 2d: 2e: 2f: 30: see note 1 31h 4 erase block region 2 information: bits 0 - 15 = y, y + 1 = number of identical-size erase blocks. bits 16 - 31 = z, region erase block(s) size are z x 256 bytes. 31: 32: 33: 34: see note 1 35h 4 reserved for future erase block region information. 35: 36: 37: 38: see note 1 note: 1. see block region map information table. table 26: block region map information address 256mb address 256mb bottom top bottom top 27: --19 --19 30: --00 --02 28: --01 --01 31: --fe --03 29: --00 --00 32: --00 --00 2a: --0a --0a 33: --00 --80 2b: --00 --00 34: --02 --00 2c: --02 --02 35: --00 --00 2d: --03 --fe 36: --00 --00 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 26: block region map information (continued) address 256mb address 256mb bottom top bottom top 2e: --00 --00 37: --00 --00 2f: --80 --00 38: --00 --00 table 27: primary vendor-specific extended query hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+0)h (p+1)h (p+2)h 3 primary extended query table, unique ascii string: pri 10a: - -50 p 10b: - -52 r 10c: - -49 i (p+3)h 1 major version number, ascii 10d: - -31 1 (p+4)h 1 minor version number, ascii 10e: - -34 4 (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1 = yes; 0 = no) bits 11 - 29 are reserved; undefined bits are 0 if bit 31 = 1, then another 31-bit field of optional features follows at the end of the bit 30 field. 10f: - -e6 C 110: - -01 C 111: - -00 C 112: see note 1 C bit 0: chip erase supported. bit 0 = 0 no bit 1: suspend erase supported. bit 1 = 1 yes bit 2: suspend program supported. bit 2 = 1 yes bit 3: legacy lock/unlock supported. bit 3 = 0 no bit 4: queued erase supported. bit 4 = 0 no bit 5: instant individual block locking supported. bit 5 = 1 yes bit 6: otp bits supported. bit 6 = 1 yes bit 7: page mode read supported. bit 7 = 1 yes bit 8: synchronous read supported. bit 8 = 1 yes bit 9: simultaneous operations supported. bit 9 = 0 no bit 10: extended flash array block supported bit 10 = 0 no bit 11: permanent block locking of up to full main array supported bit 11 = 0 no bit 12: permanent block locking of up to partial main array supported bit 12 = 0 no bit 30: cfi links to follow: bit 30 = 0 see note 1 bit 31: another optional features field to follow. bit 31 = 0 (p+9)h 1 supported functions after suspend: read ar- ray, status, query. other supported options in- clude: bits 1 - 7: reserved; undefined bits are 0. 113: - -01 C bit 0: program supported after erase suspend. bit 0 = 1 yes 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 27: primary vendor-specific extended query (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+a)h (p+b)h 2 block status register mask: bits 2 - 15 are reserved; undefined bits are 0. 114: - -03 C 115: - -00 C bit 0: block lock-bit status register active. bit 0 = 1 yes bit 1: block lock-down bit status active. bit 1 = 1 yes bit 4: efa block lock-bit status register active. bit 4 = 0 no bit 5: efa block lock-bit status active. bit 5 = 0 no (p+c)h 1 v cc logic supply highest performance program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex value in volts 116: - -18 1.8v (p+d)h 1 v pp optimum program/erase voltage. bits 0 - 3 bcd 100mv bits 4 - 7 hex value in volts 117: - -90 9.0v note: 1. see optional features fields table. table 28: optional features field address discrete 512mb bottom top bottom top C C die 1 (b) die 2 (t) die 1 (t) die 2 (b) 112: --00 --00 40: --00 --40 --00 table 29: one time programmable (otp) space information hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+e)h 1 number of otp block fields in jedec id space. 00h indicates that 256 otp fields are available. 118: - -02 2 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 29: one time programmable (otp) space information (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+f)h (p+10)h (p+11)h (p+12)h 4 otp field 1: otp description: this field describes user-available otp bytes. some are preprogrammed with device-unique se- rial numbers. others are user-programmable. bits 0-15 point to the otp lock byte (the first byte). the following bytes are factory preprogrammed and user-programmable: bits 0 - 7 = lock/bytes jedec plane physical low address. bits 8 - 15 = lock/bytes jedec plane physical high address. bits 16 - 23 = n where 2 n equals factory preprog- rammed bytes. bits 24 - 31 = n where 2 n equals user-programma- ble bytes. 119: - -80 80h 11a: - -00 00h 1b: - -03 8 byte 11c: - -03 8 byte (p+13)h (p+14)h (p+15)h (p+16)h 10 protection field 2: protection description bits 0 - 31 point to the protection register physi- cal lock word address in the jedec plane. the bytes that follow are factory or user-progam- mable. 11d: - -89 89h 11e: - -00 00h 11f: - -00 00h 120: - -00 00h (p+17)h (p+18)h (p+19)h bits 32 - 39 = n where n equals factory program- med groups (low byte). bits 40 - 47 = n where n equals factory program- med groups (high byte). bits 48 - 55 = n where 2n equals factory program- med bytes/groups. 121: - -00 0 122: - -00 0 123: - -00 0 (p+1a)h (p+1b)h (p+1c)h bits 56 - 63 = n where n equals user programmed groups (low byte). bits 64 - 71 = n where n equals user programmed groups (high byte). bits 72 - 79 = n where 2 n equals user programma- ble bytes/groups. 124: - -10 16 125: - -00 0 126: - -04 16 table 30: burst read information hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1d)h 1 page mode read capability: bits 7 - 0 = n where 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 127: - -05 32 byte 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 30: burst read information (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1e)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capabili- ty. 128: - -04 4 (p+1f)h 1 synchronous mode read capability configuration 1: bits 3 - 7 = reserved. bits 0 - 2 = n where 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maxi- mum word width. a value of 07h indicates that the device is capa- ble of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fieldss 3-bit value can be written directly to the read configuration register bits 0 - 2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 129: - -01 4 (p+20)h 1 synchronous mode read capability configuration 2. 12a: - -02 8 (p+21)h 1 synchronous mode read capability configuration 3. 12b: - -03 16 (p+22) 1 synchronous mode read capability configuration 4. 12c: - -07 continued table 31: partition and block erase region information hex offset p = 10ah description optional flash features and commands length address bottom top bottom top (p+23)h (p+23)h number of device hardware-partition regions within the device: x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions 1 12d: 12d: 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 32: partition region 1 information: top and bottom offset/address hex offset p = 10ah description optional flash features and commands length address bottom top bottom top (p+24)h (p+25)h (p+24)h (p+25)h data size of this partition region information field (number of addressable locations, including this field. 2 12e: 12e: 12f: 12f: (p+26)h (p+27)h (p+26)h (p+27)h number of identical partitions within the partition region. 2 130: 130: 131: 131: (p+28)h (p+28)h number of program or erase operations allowed in a partition: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 132: 132: (p+29)h (p+29)h simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 133: 133: (p+2a)h (p+2a)h simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 134: 134: (p+2b)h (p+2b)h types of erase block regions in this partition region: x=0: no erase blocking; the partition region erases in bulk. x = number of erase block regions with contiguous, same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks) x (type 1 block sizes) + (type 2 blocks) x (type 2 block sizes) +...+ (type n blocks) x (type n block sizes). 1 135: 135: table 33: partition region 1 information hex offset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+2c)h (p+2d)h (p+2e)h (p+2f)h partition region 1 erase block type 1 information: bits 0-15 = y, y+1 = number of identical-sized erase blocks in a partition. bits 16-31 = z, where region erase block(s) size is z x 256 bytes. 4 136: 137: 138: 139: 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 33: partition region 1 information (continued) hex offset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+30)h (p+31)h partition 1 (erase block type 1): minimum block erase cycles x 1000 2 13a: 13b: (p+32)h partition 1 (erase block type 1) bits per cell; internal ecc: bits 0 - 3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bit 5 - 7 = reserved for future use 1 13c: (p+33)h partition 1 (erase block type 1) page mode and synchronous mode capabilities: bits 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bit 3 - 7 = reserved for future use 1 13d: (p+34)h (p+35)h (p+36)h (p+37)h (p+38)h (p+39)h partition 1 (erase block type 1) programming region information: bits 0 - 7 = x, 2 x : programming region aligned size (bytes) bit 8-14 = reserved for future use bit 15 = legacy flash operation; ignore 0:7 bit 16 - 23 = y: control mode valid size (bytes) bit 24 - 31 = reserved for future use bit 32 - 39 = z: control mode invalid size (bytes) bit 40 - 46 = reserved for future use bit 47 = legacy flash operation (ignore 23:16 and 39:32) 6 13e: 13f: 140: 141: 142: 143: (p+3a)h (p+3b)h (p+3c)h (p+3d)h partition 1 erase block type 2 information: bits 0-15 = y, y+1 = number of identical-size erase blocks in a par- tition. bits 16 - 31 = z, where region erase block(s) size is z x 256 bytes. (bottom parameter device only) 4 144: 145: 146: 147: (p+3e)h (p+3f)h partition 1 (erase block type 2) minimum block erase cycles x 1000 2 148: 149: (p+40)h partition 1 (erase block type 2) bits per cell, internal edac: bits 0 - 3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5 - 7 = reserved for future use 1 14a: (p+41)h partition 1 (erase block type 2) page mode and synchronous mode capabilities: bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use 1 14b: 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 33: partition region 1 information (continued) hex offset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+42)h (p+43)h (p+44)h (p+45)h (p+46)h (p+47)h partition 1 (erase block type 2) programming region information: bits 0-7 = x, 2 n x = programming region aligned size (bytes) bits 8-14 = reserved for future use bit 15 = legacy flash operation (ignore 0:7) bits 16 - 23 = y = control mode valid size in bytes bits 24 - 31 = reserved bits 32 - 39 = z = control mode invalid size in bytes bits 40 - 46 = reserved bit 47 = legacy flash operation (ignore 23:16 and 39:32) 6 14c: 14d: 14e: 14f: 150: 151: 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 34: partition region 1: partition and erase block map information address 256mb bottom top 12d: - -01 - -01 12e: - -24 - -24 12f: - -00 - -00 130: - -01 - -01 131: - -00 - -00 132: - -11 - -11 133: - -00 - -00 134: - -00 - -00 135: - -02 - -02 136: - -03 - -fe 137: - -00 - -00 138: - -80 - -00 139: - -00 - -02 13a: - -64 - -64 13b: - -00 - -00 13c: - -02 - -02 13d: - -03 - -03 13e: - -00 - -00 13f: - -80 - -80 140: - -00 - -00 141: - -00 - -00 142: - -00 - -00 143: - -80 - -80 144: - -fe - -03 145: - -00 - -00 146: - -00 - -80 147: - -02 - -00 148: - -64 - -64 149: - -00 - -00 14a: - -02 - -02 14b: - -03 - -03 14c: - -00 - -00 14d: - -80 - -80 14e: - -00 - -00 14f: - -00 - -00 150: - -00 - -00 151: - -80 - -80 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 35: cfi link information offset p = 10ah length description address ascii value (dq[7:0]) cfi link field bit definitions: (p+48)h 4 bits 0 - 9 = address offset (within 32mbit segment of refer- enced cfi table) 152: see note 1 (p+49)h bits 10 - 27 = nth 32mbit segment of referenced cfi table 153: (p+4a)h bits 28 - 30 = memory type 154: (p+4b)h bit 31 = another cfi link field immediately follows 155: (p+4c)h 1 cfi link field quantity subfield definitions: bits 0 - 3 = quantity field (n such that n+1 equals quantity) bit 4 = table and die relative location bit 5 = link field and table relative location bits 6 - 7 = reserved 156: note: 1. see additional cfi link field table. table 36: additional cfi link field address discrete 512mb bottom top bottom top C C die 1 (b) die 2 (t) die 1 (t) die 2 (b) 152: --ff --ff --10 --ff --10 --ff 153: --ff --ff --20 --ff --20 --ff 154: --ff --ff --00 --ff --00 --ff 155: --ff --ff --00 --ff --00 --ff 156: --ff --ff --10 --ff --10 --ff 256mb and 512mb (256mb/256mb), p30-65nm common flash interface pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
flowcharts figure 17: word program procedure no progam complete d7 = 1? command cycle - issue program command - address = location to program - data = 0x40 start program suspend (see suspend/resume flowchart yes yes yes no no suspend? data cycle - address = location to program - data = data to program check ready status - read status register command not required - perform read operation - read ready status on signal d7 errors? read status register - toggle ce# or oe# to update status register - see status register flowchart error-handler user-defined routine 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 18: buffer program procedure yes device ready? sr7 = 0/1 set timeout or loop counter start use single word programming get next target address read status register sr7 = valid (at block address ) timeout or count expired? issue write-to-buffer command e8h (at block address) x = 0 write confirm d0h (at block address) (at block address) read status register device supports buffer writes? write word count (n-1) (at block address) write buffer data, start address write buffer data, (at block address) within buffer range x = x + 1 no no 0 = no no yes yes no yes 1 = yes x = n abort bufferred program ? 0 full status check (if desired) 1 sr7? suspend program no another buffered programming ? program complete write to another block address suspend program loop buffered program aborted yes 1 = ready 0 = busy n = 0 corresponds to count = 1 ce# and oe# low updates status register no yes notes: 1. word count values on dq0:dq15 are loaded into the count register. count ranges for this device are n = 0000h to 01ffh. 2. device outputs the status register when read. 3. write buffer contents will be programmed at the device start or destination address. 4. align the start address on a write buffer boundary for maximum programming perform- ance; that is, a[9:1] of the start address = 0). 5. device aborts the buffered program command if the current address is outside the original block address. 6. status register indicates an improper command sequence if the buffered program command is aborted. follow this with a clear status register command. 7. device defaults to sr output data after buffered programming setup command (e8h) is issued . ce# or oe# must be toggled to update the status register . dont issue the read sr command (70h); it is interpreted by the device as buffer word count. 8. full status check can be done after erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 19: buffered enhanced factory programming (befp) procedure no (sr7 = 1) yes (sr7 = 0) yes (sr0 = 0) befp setup done? issue befp setup data = 0x80 start exit issue befp confirm data = 00d0h befp setup delay read status register sr error-handler user-defined yes no buffer full? buffer ready? read status register register write data word to buffer read status register program done? no yes program more data ? write 0xffff outside block setup phase program and verify phase exit phase finish yes (sr7 = 1) no (sr7 = 0) befp exited? full status register check for errors no (sr0 = 1) no (sr0 = 1) yes (sr0 = 0) read status 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 20: block erase procedure start sr7 = 1? erase suspend see suspend/ resume flowchart error handler user-defined routine end command cycle - issue erase command - address = block to be erased - data = 0x20 yes yes no no suspend? confirm cycle check ready status - issue confirm command - address = block to be erased - data = erase confirm (0xd0) - read status register command not required - perform read operation - read ready status on sr7 no yes errors? read status register - toggle ce# or oe# to update status register - see status register flowchart 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 21: program suspend/resume procedure read status register = sr2 sr7 = read array data program completed done reading program resumed read array data 0 no 0 yes 1 1 start write b0h any address program suspend read status write 70h write ffh any address read array write d0h any address program resume write ffh read array write 70h any address read status any address 1 = ready 0 = busy 1 = suspended 0 = completed (address = block to suspend) update the status register initiate read cycle to from a block other than programmed from the one being 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 22: erase suspend/resume procedure read status register = sr6 sr7 = read/program? erase completed done? erase resumed read array data 0 0 yes no 1 1 start write b0h any address erase suspend read status write 70h write d0h any address erase resume write ffh read array write 70h any address read status any address 1 = suspended 0 = completed 1 = ready 0 = busy (ffh/40h) address = x toggle ce#/oe# to update the status register read program read array data from a block other than the one being erased program loop: to a block other than the one being erased 1 note: 1. the t ers/susp timing between the initial block erase or erase resume command and a subsequent erase suspend command should be followed. 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 23: block lock operations procedure write 90h read block lock status locking change? lock change complete no yes start write 01h, d0h, 2fh block address lock confirm read id plane lock setup write 60h write ffh any address read array block address optional 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 24: otp register programming procedure start sr7 = 1? end otp program setup - write 0xc0 - otp address yes no confirm data - write otp address and data check ready status - read status register command not required - perform read operation - read ready status on sr7 read status register - toggle ce# or oe# to update status register - see status register flowchart 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 25: status register procedure erase suspend see suspend/ resume flowchart set/reset by device - set by device - reset by user - see clear status register command start end command cycle - issue status register command - address = any device address - data = 0x70 data cycle - read status register sr[7:0] yes yes yes no no no yes yes no no sr7 = 1 sr6 = 1 sr2 = 1 sr5 = 1 sr4 = 1 sr4 = 1 sr3 = 1 sr1 = 1 no yes yes yes no no program suspend see suspend/ resume flowchart error erase failure error command sequence error program failure error v pen /v pp < v penlk /v pplk error block locked 256mb and 512mb (256mb/256mb), p30-65nm flowcharts pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
power and reset specifications v cc should attain v ccmin from v ss simultaneously with or before applying v ccq , v pp during power up. v cc should attain v ss during power down. device inputs should not be driven before supply voltage = v ccmin . power supply transitions should only occur when rst# is low. this protects the device from accidental programming or erasure during power transitions. asserting rst# during a system reset is important with automated program/erase devi- ces because systems typically expect to read from the device when coming out of reset. if a cpu reset occurs without a device reset, proper cpu initialization may not occur. this is because the device may be providing status information, instead of array data as expected. connect rst# to the same active low reset signal used for cpu initialization. because the device is disabled when rst# is asserted, it ignores its control inputs dur- ing power-up/down. invalid bus conditions are masked, providing a level of memory protection. table 37: power and reset parameter symbol min max unit notes rst# pulse width low t plph 100 C ns 1, 2, 3, 4 rst# low to device reset during erase t plph C 25 us 1, 3, 4, 7 rst# low to device reset during program C 25 1, 3, 4, 7 v cc power valid to rst# de-assertion (high) t vccph 300 C 1, 4, 5, 6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to v cc . 4. sampled, but not 100% tested. 5. when rst# is tied to the v cc supply, device will not be ready until t vccph after v cc v ccmin . 6. when rst# is tied to the v ccq supply, device will not be ready until t vccph after v cc v ccmin . 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing. 256mb and 512mb (256mb/256mb), p30-65nm power and reset specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 26: reset operation waveforms (a) reset during read mode v ih v il rst# (d) v cc power-up to rst# high t plph t phqv t phqv t phqv v cc 0v v cc t vccph (b) reset during program or block erase p1 p2 v ih v il rst# abort complete abort complete t plrh (c) reset during program or block erase p1 p2 v ih v il rst# t plrh power supply decoupling the device requires careful power supply de-coupling. three basic power supply cur- rent considerations are 1) standby current levels, 2) active current levels, and 3) transi- ent peaks produced when ce# and oe# are asserted and de-asserted. when the device is accessed, internal conditions change. circuits within the device ena- ble charge pumps, and internal logic states change at high speed. these internal activi- ties produce transient signals. transient current magnitudes depend on the device out- puts capacitive and inductive loading. two-line control and correct de-coupling capac- itor selection suppress transient voltage peaks. because the devices draw their power from v cc , v pp , and v ccq , each power connection should have a 0.1f and a 0.01f ceramic capacitor to ground. high-frequency, inher- ently low-inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. 256mb and 512mb (256mb/256mb), p30-65nm power and reset specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
maximum ratings and operating conditions stresses greater than those listed can cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other condi- tions above those indicated is not guaranteed. table 38: maximum ratings parameter maximum rating notes temperature under bias C40c to + 85 c storage temperature C65c to + 125 c voltage on any signal (except v cc , v pp , and v ccq ) C2v to +4v 1 v pp voltage C2v to +11.5v 1, 2 v cc voltage C2v to +4v 1 v ccq voltage C2v to +5.6v 1 output short circuit current 100ma 3 notes: 1. voltages shown are specified with respect to v ss . during infrequent nonperiodic transi- tions, the level may undershoot to C2v for periods less than 20ns or overshoot to v cc + 2v or v ccq + 2v or v pp + 2v for periods less than 20ns. 2. program/erase voltage is typically 1.7C2v; 9v can be applied for 80 hours maximum to- tal, however, 9v program/erase voltage may reduce block cycling capability. 3. output is shorted for no more than one second, and more than one output is not shor- ted at one time. table 39: operating conditions symbol parameter min max unit notes t a operating temperature C40 +85 c 1 v cc v cc supply voltage 1.7 2 v v ccq i/o supply voltage cmos inputs 1.7 3.6 ttl inputs 2.4 3.6 v ppl v pp voltage supply (logic level) 0.9 3.6 2 v pph buffered enhanced factory programming v pp 8.5 9.5 t pph maximum v pp hours v pp = v pph C 80 hours block erase cycles main and parameter blocks v pp = v ppl 100,000 C cycles main blocks v pp = v pph C 1000 parameter blocks v pp = v pph C 2500 notes: 1. t a = ambient temperature. 2. in typical operation, v pp program voltage is v ppl . 256mb and 512mb (256mb/256mb), p30-65nm maximum ratings and operating conditions pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dc electrical specifications table 40: dc current characteristics parameter symbol cmos inputs (v ccq = 1.7C 3.6v) ttl inputs (v ccq = 2.4C 3.6v) unit test conditions notes typ max typ max input load current i li C 1 C 2 a v cc = v cc (max) v ccq = v ccq (max) v in = v ccq or v ss 1, 6 output leakage current dq[15:0], wait i lo C 1 C 10 a v cc = v cc (max) v ccq = v ccq (max) v in = v ccq or v ss v cc standby, power-down 256mb i ccs , i ccd 65 210 65 210 a v cc = v cc (max) v ccq = v ccq (max) ce# = v ccq rst# = v ccq (for i ccs ) rst# = v ss (for i ccd ) wp# = v ih 1. 2 512mb 130 420 130 420 average v cc read current asynchronous sin- gle-word f = 5 mhz (1 clk) i ccr 26 31 26 31 ma 16-word read v cc = v cc (max) ce# = v il oe# = v ih inputs: v il or v ih 1 12 16 12 16 ma 16-word read 19 22 19 22 ma 8-word read page mode read f = 13 mhz (17 clk) 16 18 16 18 ma 16-word read synchronous burst f = 52 mhz, lc = 4 21 24 21 24 ma continuous read v cc program current, v cc erase current i ccw, i cce 35 50 35 50 ma v pp = v ppl , program/erase in progress 1, 3, 5 35 50 35 50 v pp = v pph , program/erase in progress 1, 3, 5 v cc program sus- pend current, v cc erase suspend current 256mb i ccws, i cces 65 210 65 210 a ce# = v ccq , suspend in pro- gress 1, 3, 4 512mb 70 225 70 225 v pp standby current, v pp program suspend current, v pp erase suspend current i pps, i ppws, i ppes 0.2 5 0.2 5 a v pp = v ppl , suspend in progress 1, 3, 7 v pp read i ppr 2 15 2 15 a v pp = v ppl 1, 3 v pp program current i ppw 0.05 0.1 0.05 0.1 ma v pp = v ppl , program in progress 3 0.05 0.1 0.05 0.1 v pp = v pph , program in pro- gress v pp erase current i ppe 0.05 0.1 0.05 0.1 ma v pp = v ppl , erase in progress 3 0.05 0.1 0.05 0.1 v pp = v pph , erase in progress 256mb and 512mb (256mb/256mb), p30-65nm dc electrical specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 40: dc current characteristics (continued) parameter symbol cmos inputs (v ccq = 1.7C 3.6v) ttl inputs (v ccq = 2.4C 3.6v) unit test conditions notes typ max typ max v pp blank check i ppbc 0.05 0.1 0.05 0.1 ma v pp = v ppl 3 0.05 0.1 0.05 0.1 v pp = v pph notes: 1. all currents are rms unless noted. typical values at typ v cc , t c = +25c. 2. i ccs is the average current measured over any 5ms time interval 5s after ce# is de-asser- ted. 3. sampled, not 100% tested. 4. i cces is specified with the device deselected. if device is read while in erase suspend, cur- rent is i cces plus i ccr . 5. i ccw , i cce measured over typ or max times specified in program and erase characteris- tics (page 97). 6. if v in > v cc , the input load current increases to 10a max. 7. the i pps, i ppws, i ppes will increase to 200a when v pp /wp# is at v pph . table 41: dc voltage characteristics parameter symbol cmos inputs (v ccq = 1.7C3.6v) ttl inputs 1 (v ccq = 2.4C3.6v) unit test conditions notes min max min max input low voltage v il C0.5 0.4 C0.5 0.6 v 2 input high voltage v ih v ccq - 0.4 v ccq + 0.5 2 v ccq + 0.5 v output low voltage v ol C 0.2 C 0.2 v v cc = v cc (min) v ccq = v ccq (min) i ol = 100a output high voltage v oh v ccq - 0.2 C v ccq C 0.2 C v v cc = v cc (min) v ccq = v ccq (min) i oh = C100a v pp lock out voltage v pplk C 0.4 C 0.4 v 3 v cc lock voltage v lko 1.5 C 1.5 C v v ccq lock voltage v lkoq 0.9 C 0.9 C v notes: 1. synchronous read mode is not supported with ttl inputs. 2. v il can undershoot to C1.0v for durations of 2ns or less and v ih can overshoot to v ccq + 1.0v for durations of 2ns or less. 3. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges. 256mb and 512mb (256mb/256mb), p30-65nm dc electrical specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac test conditions and capacitance figure 27: ac input/output reference timing input v ccq /2 v ccq /2 output v ccq 0v test points note: 1. ac test inputs are driven at v ccq for logic 1 and at 0v for logic 0. input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) <5ns. worst-case speed oc- curs at v cc = v cc (min). figure 28: transient equivalent load circuit device under test out c l notes: 1. see the test configuration for worst-case speed conditions table for component values. 2. cl includes jig capacitance. table 42: test configuration: worst-case speed condition test configuration c l (pf) v ccq (min) standard test 30 figure 29: clock input ac waveform t fclk/rclk clk t ch/cl v ih v il t clk 256mb and 512mb (256mb/256mb), p30-65nm ac test conditions and capacitance pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 43: capacitance parameter signal density min typ max unit condition notes input capacitance address, data, ce#, we#, oe#, rst#, clk, adv#, wp# 256mb 3 7 8 pf typ temp = 25c; max temp = 85c v cc = 0C2.0v, v ccq = 0C 3.6v discrete silicon die 1 256mb/ 256mb 6 14 16 output capacitance data, wait 256mb 3 5 7 256mb/ 256mb 6 10 14 note: 1. sampled, but not 100% tested. 256mb and 512mb (256mb/256mb), p30-65nm ac test conditions and capacitance pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac read specifications table 44: ac read specifications parameter symbol min max unit notes asynchronous specifications read cycle time t avav easy bga quad+ 100 C ns C tsop 110 C address to output valid t avqv easy bga quad+ C 100 ns C tsop C 110 ce# low to output valid t elqv easy bga quad+ C 100 ns C tsop C 110 oe# low to output valid t glqv C 25 ns 1, 2 rst# high to output valid t phqv C 150 ns 1 ce# low to output in low-z t elqx 0 C ns 1, 3 oe# low to output in low-z t glqx 0 C ns 1, 2, 3 ce# high to output in high-z t ehqz C 20 ns 1, 3 oe# high to output in high-z t ghqz C 15 output hold from first occurring address, ce#, or oe# change t oh 0 C ce# pulse width high t ehel 17 C ns 1 ce# low to wait valid t eltv C 17 ce# high to wait high-z t ehtz C 20 ns 1, 3 oe# low to wait valid t gltv C 17 ns 1 oe# low to wait in low-z t gltx 0 C ns 1, 3 oe# high to wait in high-z t ghtz C 20 latching specifications address setup to adv# high t avvh 10 C ns 1 ce# low to adv# high t elvh 10 C adv# low to output valid t vlqv easy bga quad+ C 100 ns 1 tsop 110 adv# pulse width low t vlvh 10 C ns 1 adv# pulse width high t vhvl 10 C address hold from adv# high t vhax 9 C ns 1, 4 page address access t apa C 25 ns 1 rst# high to adv# high t phvh 30 - clock specifications 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 44: ac read specifications (continued) parameter symbol min max unit notes clk frequency t clk easy bga quad+ C 52 mhz 1, 3, 5, 6 tsop 40 clk period t clk easy bga quad+ 19.2 C ns 1, 3, 5, 6 tsop 25 clk high/low time t ch/cl easy bga quad+ 5 C ns 1, 3, 5, 6 tsop 9 clk fall/rise time t fclk/rclk 0.3 3 ns 1, 3, 5, 6 synchronous specifications 5 address setup to clk t avch/l 9 C ns 1, 6 adv# low setup to clk t vlch/l 9 C ce# low setup to clk t elch/l 9 C clk to output valid t chqv / t clqv easy bga quad+ C 17 ns 1, 6 tsop 20 output hold from clk t chqx 3 - ns 1, 6 address hold from clk t chax 10 - ns 1, 4, 6 clk to wait valid t chtv easy bga quad+ C 17 ns 1, 6 tsop 20 clk valid to adv# setup t chvl 3 C ns 1 wait hold from clk t chtx easy bga quad+ 3 C ns 1, 6 tsop 5 notes: 1. see ac test conditions for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv C t glqv after ce#s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax, whichever timing specifica- tion is satisfied first. 5. synchronous read mode is not supported with ttl level inputs. 6. applies only to subsequent synchronous reads. 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 30: asynchronous single-word read (adv# low) a t ava v adv# ce# oe# w ait dq rst# t a vqv t elqv t glqv t g l tv t glqx t elqx t phqv t ehqz t ghqz t ghtz note: 1. wait shown deasserted during asynchronous read mode (rcr10 = 0, wait asserted low). figure 31: asynchronous single-word read (adv# latch) a[4:1] a[max:5] ce# oe# wait dq adv# t elqx t glqv t elqv t ehqz t ghqz t ghtz t oh t avav t avqv t vhvl t avvh t gltv t glqx t vhax note: 1. wait shown deasserted during asynchronous read mode (rcr10 = 0, wait asserted low). 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 32: asynchronous page mode read a[max:5] a[4:1] adv# t avqv t vhax t vhvl t avvh ce# oe# wait dq t ehtz t oh t oh t oh t apa t elqx t apa t apa t elqv t glqv valid address 1 0 2 f q1 q2 q3 q16 t oh t ehqz t ghqz note: 1. wait shown deasserted during asynchronous read mode (rcr10 = 0, wait asserted low). 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 33: synchronous single-word array or nonarray read clk ce# oe# w ait dq adv# a t a vch t chax t a vqv t a vvh t v l vh t elch t e l vh t elqv t glqx t gltx t ghqz t ehqz t chtx t glqv t chqv t chqx t ghtz t chtv t vhax t vhvl notes: 1. wait is driven per oe# assertion during synchronous array or nonarray read and can be configured to assert either during or one data cycle before valid data. 2. in this example, an n -word burst is initiated to the flash memory array and is terminated by ce# deassertion after the first word in the burst. 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 34: continuous burst read with output delay a clk adv# ce# oe# wait dq t vlch t avch t avvh t avqv t chax t chqv t chqv t chqv t chtx t chtv t chqv t glqx t glqv t elch t chqx t chqx t chqx t chqx t elvh t elqv t gltx t vhvl t vhax notes: 1. wait is driven per oe# assertion during synchronous array or nonarray read and can be configured to assert either during or one data cycle before valid data. 2. at the end of a wordline; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 35: synchronous burst mode 4-word read a clk adv# ce# oe# wait dq t vlch t avch latency count t avvh t avqv t chax t ghtz t chtv t ghqz t chqv t chqv t glqx t glqv t oh t chqx t elvh t elqv t gltv t vhvl t vhax a t elch t ehqz q0 q1 q2 q3 note: 1. wait is driven per oe# assertion during synchronous array or nonarray read. wait as- serted during initial latency and deasserted during valid data (rcr10 = 0, wait asserted low). 256mb and 512mb (256mb/256mb), p30-65nm ac read specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac write specifications table 45: ac write specifications parameter symbol min max unit notes rst# high recovery to we# low t phwl 150 - ns 1, 2, 3 ce# setup to we# low t elwl 0 - ns 1, 2, 3 we# write pulse width low t wlwh 50 - ns 1, 2, 4 data setup to we# high t dvwh 50 - ns 1, 2, 12 address setup to we# high t avwh 50 - ns 1, 2 ce# hold from we# high t wheh 0 - ns data hold from we# high t whdx 0 - ns address hold from we# high t whax 0 - ns we# pulse width high t whwl 20 - ns 1, 2, 5 v pp setup to we# high t vpwh 200 - ns 1, 2, 3, 7 v pp hold from status read t qvvl 0 - ns wp# hold from status read t qvbl 0 - ns 1, 2, 3, 7 wp# setup to we# high t bhwh 200 - ns we# high to oe# low t whgl 0 - ns 1, 2, 9 we# high to read valid t whqv t avqv + 35 - ns 1, 2, 3, 6, 10 write to asynchronous read specifications we# high to address valid t whav 0 - ns 1, 2, 3, 6, 8 write to synchronous read specifications we# high to clock valid t whch/l 19 - ns 1, 2, 3, 6, 10 we# high to adv# high t whvh 19 - ns we# high to adv# low t whvl 7 - ns write specification with clock active adv# high to we# low t vhwl - 20 ns 1, 2, 3, 11 clock high to we# low t chwl - 20 ns notes: 1. write timing characteristics during erase suspend are the same as write-only opera- tions. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low ( t wlwh or t eleh) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). thus, t wlwh = t eleh = t wleh = t elwh. 5. write pulse width high t whwl or t ehel) is defined from ce# or we# high whichever occurs first) to ce# or we# low whichever occurs last). thus, t whwl = t ehel = t whel = t ehwl). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchro- nous burst read. 7. v pp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asyn- chronous read. see spec t whch/l and t whvh for synchronous read. 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
9. when doing a read status operation following any command that alters the status register, t whgl is 20ns. 10. add 10ns if the write operation results in an rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and the clock is active during an address setup phase. 12. this specification must be complied with customers writing timing. the result would be unpredictable if there is any violation to this timing specification. 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 36: write to write timing figure 37: asynchronous read to write timing a t avav ce# oe# wait we# dq rst# t avqv t whax t avwh t elqv t ehqz t glqv t glqx t whdx t elqx t oh q d t dvwh t phqv t ghqz t elwl t gltv t ghtz t wlwh t wheh note: 1. wait de-asserted during asynchronous read and during write. wait high-z during write per oe# deasserted. 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 38: write to asynchronous read timing 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 39: synchronous read to write timing a clk adv# ce# oe# we# wait dq t vlch t avch latency count t avvh t avqv t whav t avwh t vlvh t chax t chtv t glqx t glqv t whdx t vlwh t wlwh t elwl t chwl t whwl t chwl t whax t vhwl t vhwl t chqx t elvh t elqv t gltx t vhvl t vhax t elch t ehel t ehtz t wheh t ghqz d d q t chqv t chtx note: 1. wait shown de-asserted and high-z per oe# de-assertion during write operation (rcr10 = 0, wait asserted low). clock is ignored during write operation. 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 40: write to synchronous read timing a clk adv# ce# we# oe# w ait dq rst# t a vch t vlch t chax t whax t a vwh t a vqv latency count t chtv t g l tx t elch t wheh t whvh t w l wh t glqv t whch/l t wh a v t chqv t elqv t whdx t dvwh t phwl t chqx t chqv t ehel t e l wl t v l vh t vhax d q q note: 1. wait shown de-asserted and high-z per oe# de-assertion during write operation (rcr10 = 0, wait asserted low). 256mb and 512mb (256mb/256mb), p30-65nm ac write specifications pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program and erase characteristics table 46: program and erase specifications parameter symbol v ppl v pph unit notes min typ max min typ max conventional word programming program time single word t prog/w C 270 456 C 270 456 s 1 buffered programming program time aligned, bp time (32 words) t prog C 310 716 C 310 716 s 1 aligned, bp time (64 words) C 310 900 C 310 900 aligned, bp time (128 words) C 375 1140 C 375 1140 aligned, bp time (256 words) C 505 1690 C 505 1690 one full buffer, bp time (512 words) C 900 3016 C 900 3016 buffered enhanced factory programming program single byte t befp/b n/a n/a n/a C 0.5 C s 1, 2 befp setup t befp/setup n/a n/a n/a 5 C C 1 erase and suspend erase time 32kb parameter t ers/pb C 0.8 4.0 C 0.8 4.0 s 1 128kb main t ers/mb C 0.8 4.0 C 0.8 4.0 suspend la- tency program suspend t susp/p C 25 30 C 25 30 s erase suspend t susp/e C 25 30 C 25 30 erase-to-suspend t ers/susp C 500 C C 500 C 1, 3 blank check blank check main array block t bc/mb C 3.2 C C 3.2 C ms notes: 1. typical values measured at t c = +25c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. averaged over entire device. 3. t ers/susp is the typical time between an initial block erase or erase resume com- mand and the a subsequent erase suspend command. violating the specification re- peatedly during any particular block erase may cause erase failures. 256mb and 512mb (256mb/256mb), p30-65nm program and erase characteristics pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
revision history rev. c C 12/13 ? on cover page, corrected erase suspend (typ) from 30 s to 25 s. ? added the following part number disclaimer: "not all part numbers listed here are available for ordering." ? revised timings rev. b C 8/13 ? format and organization edits rev. a C 10/12 ? initial micron brand release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256mb and 512mb (256mb/256mb), p30-65nm revision history pdf: 09005aef84566799 p30_65nm_mlc_256mb-512mb.pdf - rev. c 12/13 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.

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